Skip to content
STIMSMITH

STIMSMITH

stimulus knowledge
knowledge graph warming up…
explore via search or browse
most connected
RISC-V
Concept · 213 links
6,672
entities
10,906
relationships
+76 entities · +91 links — latest run (2026-07-20)
activity
01
Challenges in CSR Design and Verification Signoff

Processed 32 entities and 31 relations.

32 ent archive
System-on-Chip Hardware-Software Interface Control and Status Registers General-Purpose Registers Clock Domain Crossing Parity Error-Correcting Code Cyclic Redundancy Check Triple Module Redundancy RTL Universal Verification Methodology Object-Oriented Programming Constrained-Random Stimulus Generation Functional Coverage Verification Signoff Coverage Closure Regression Test Stimulus Constraints Test Sequences Testbench IP Core Device Driver Bus Interface APB AHB AXI4 TileLink IDesignSpec Suite Agnisys Executable Golden Specification Coverage Point Design Tape-Out
02
Guiding Greybox Fuzzing with Mutation Testing

Processed 44 entities and 60 relations.

44 ent archive
Mu2 Zest JQF PIT AFL libFuzzer OSS-Fuzz Greybox Fuzzing Coverage-Guided Greybox Fuzzing Mutation Testing Mutation-Analysis-Guided Fuzzing Differential Testing Coverage-Guided Property Testing Mutation Score Code Coverage Program Mutant Test Adequacy PIE Model Execution-Based Pruning Infection-Based Pruning Fuzzing Oracle Regression Testing Fuzzing Corpus Mutant Pruning k-Least-Executed Mutant Filter k-Random Mutant Filter CoverageClassLoader MutationClassLoader Guiding Greybox Fuzzing with Mutation Testing Vasudev Vikram Rohan Padhye Isabella Laybourn Ao Li Nicole Nair Kelton OBrien Rafaello Sanna Carnegie Mellon University Google Google Closure Compiler ChocoPy Gson Jackson Apache Tomcat Mu2 Source Code
03
Low Power, High Risk: Fuzzing the Chips Behind IoT

Processed 52 entities and 55 relations.

52 ent archive
Fuzzing Coverage-Guided Fuzzing Firmware Fuzzing MMIO Modeling Emulation-Based Fuzzing Crash Bucket Analysis Crash Trace Replay Fault Injection Voltage Glitching Debug Mode MMIO Injection Static MMIO Read Patching Delay Function Patching Reverse Engineering Proof-of-Concept Exploit Development Fuzzware QEMU Unicorn Engine Ghidra nrfjprog Aurora-Fuzz Aurora-Fuzz Configuration Script Memory-Mapped I/O (MMIO) Instruction Pointer Link Register Stack Pointer UICR FICR Coverage Feedback Translation Blocks Remote Code Execution Denial of Service Stack Overflow Raw Input ISA Emulator Interrupt DMA Fuzzware: Using Precise MMIO Modeling for Effective Firmware Fuzzing Tobias Scharnowski Nils Bars Moritz Schloegel Eric Gustafson Marius Muench Giovanni Vigna Christopher Kruegel Thorsten Holz Ali Abbasi Noah Holmdin Ravishankar Borgaonkar SINTEF NTNU Nordic Semiconductor nRF52840 Development Kit
04
Late Breaking Results: Float Fight - Verifying

Processed 37 entities and 51 relations.

37 ent archive
FP-RVVTS RVVTS RISCV-DV Spike Spike FF RISC-V VP++ QEMU SoftFloat FloppyFloat riscvOVPsim context-free grammar specification single-instruction isolation dependency annotation constrained-random instruction generation negative testing positive testing functional coverage measurement failure cause analysis RISC-V FP extensions IEEE 754 floating-point arithmetic instruction set architecture RISC-V Instruction Sequence Generator rounding mode NaN handling Float Fight: Verifying Floating-Point Behavior in RISC-V Simulators Single instruction isolation for RISC-V vector test failures FloppyFloat: An open source floating point library for instruction set simulators RISC-V VP++: Next generation open-source virtual prototype Katharina Ruep Manfred Schlägl Daniel Große Johannes Kepler University Linz UC Berkeley RISC-V International Google
05
Single Instruction Isolation for RISC-V Vector Test Failures

Processed 57 entities and 62 relations.

57 ent archive
Single Instruction Isolation for RISC-V Vector Test Failures Manfred Schlägl Daniel Große Johannes Kepler University RISC-V RISC-V Vector Extension (RVV) RVVTS Single Instruction Isolation with Code Minimization RISC-V VP++ QEMU Instruction Sequence Generator (ISG) RISCV-DV Google FORCE-RISCV OpenHW Group positive testing negative testing Device Under Test (DUT) functional coverage coverage-guided test generation constraint solving for test generation grammar-based ISG Machine State Code Fragment Code Block CodeErrMinRunner CovGuidedTestsetGenerator CodeCompareRunner TestsetCodeErrMinRunner RefCovRunner GDBRunner CodeCheckRunner Spike riscvOVPsim Imperas Delta Code Reduction (Binary Search) Valid Sequences (VS) test set Invalid+Valid Sequences (IVS) test set Merged Sequences (MS) test set Execution Runner Symbolic Quick Error Detection (SQED) Bounded Model Checking (BMC) coverage-guided fuzzing Universal Verification Methodology (UVM) RTL SIMD RISC-V Sail specification model Program Counter (PC) Control and Status Register (CSR) GDB Remote Debug Protocol (RDB) Executable and Linkable Format (ELF) RISC-V compliance test suite EPEX Jupyter notebooks Instruction Set Simulator (ISS) Virtual Prototype (VP) bounded load/store operations
06
CAMBRIDGE

Processed 35 entities and 35 relations.

35 ent archive
TestRIG RVFI-DII QuickCheckVEngine QuickCheck Sail RISC-V CHERI tandem verification mutation coverage code coverage randomised testing random instruction generation RVFI trace golden model executable simulator test shrinking microarchitectural mutation coverage RTL SQLite Sail JAL semantics Toooba CVA6 Microsoft Research lowRISC SCI Semiconductor University of Cambridge SRI International Peter Rugg Alexandre Joannou Jonathan Woodruff Franz A. Fuchs Simon W. Moore DII (Direct Instruction Injection) hardware capabilities memory safety
01
RISC-V Verification: 5 Places Projects Lose Weeks

Processed 43 entities and 42 relations.

43 ent archive
RISC-V ISA scope RISC-V profiles custom instructions random instruction generation constrained-random stimulus generation functional coverage coverage model lockstep co-simulation reference model formal verification directed tests architectural certification tests instruction retirement comparison debug visibility trace infrastructure privilege modes CSR interactions exception handling interrupt handling SoC integration verification software-facing verification coverage closure verification plan RTL UVM pipeline hazards PMP protection features debug mode riscv-dv Sail RISC-V model RISCOF riscv-arch-test riscv-formal RISC-V International OpenHW Group CHIPS Alliance YosysHQ Alpinum Consulting RISC-V Instruction Set Manual Volume I RISC-V Debug Specification CORE-V Verification Strategy CORE-V
02
A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking

Processed 42 entities and 48 relations.

42 ent archive
A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking Mike G. Bartley Darren Galpin Tim Blackmore Elixent Ltd Infineon Technologies UK Ltd Directed Testing Pseudo-Random Testing Property Checking Specman Elite GateProp Bus Functional Model (BFM) e Language Verification Component (eVC) Design Under Test (DUT) LFI Bus Bridge LFI-IBC32 LFI-S Local Memory Bus (LMB) Flexible Peripheral Interface Bus (FPI) Functional Coverage Structural Coverage FSM Transition Coverage Protocol Checker Formal Verification Constraint-Driven Testing Transaction Coverage Bus Protocol Properties Transaction Properties Toggle Coverage State Space Explosion Verification IP Reuse Semi-Formal Verification 0-In Search Verisity Accellera Siemens Register-Transfer Level (RTL) VHDL Black Box Test Specification White Box Testing Bug Curve Advanced High-performance Bus (AHB)
03
PORTRUSH: Detect Write Port Contention

Processed 55 entities and 60 relations.

55 ent archive
PORTRUSH Write Port Contention Write Request Graph Hierarchical Aggregation and Decoding Contention-guided Hardware Fuzzing Hardware Fuzzing Transient Execution Attack Side-Channel Attack Speculative Execution Register-Transfer Level BOOM NutShell Rocket Core RISC-V Particle Swarm Optimization Differential Testing Assertion-Based Verification Seed Corpus Register Coverage Write Request Behavior Coverage Signal Decoder Signal Aggregation Engine Out-of-Order Execution Cache Side-Channel Attack FLUSH+RELOAD PRIME+PROBE Evict+Time SMoTherSpectre Spectre-STC MSHRush Birgus-variant FIRRTL Compiler SpecDoctor Reorder Buffer Miss Status Holding Register Register File Priority Arbitration Formal Verification Multiplexer Instruction Sequence Mutation Seed Minimization National University of Defense Technology Peihong Lin Pengfei Wang Lei Zhou Gen Zhang Xu Zhou Wei Xie Zhiyuan Jiang Kai Lu Design Under Test Kernel Page-Table Isolation Chisel Depth-First Search Binary Search Seed Minimization
04
SiliFuzz: Fuzzing CPUs by proxy

Processed 57 entities and 86 relations.

57 ent archive
SiliFuzz Fuzzing Coverage-Guided Mutation-Based Fuzzing Generation-Based Fuzzing Blackbox Fuzzing Greybox Fuzzing Structure-Aware Fuzzing Differential Testing Proxy-Based Fuzzing Corpus Distillation Snapshot-Based Testing Nondeterminism Elimination Register Scrambling Cross-Pollination of Corpora libFuzzer AFL Honggfuzz Syzkaller XED Unicorn ifuzz Sandsifter UISFuzz gem5 Simics SiliFuzz Checker Silent Data Corruption CPU Logic Bug CPU Electrical Defect Code Coverage Snapshot Fuzzing Corpus Instruction Sequence Generation x86_64 Instruction Encoding Fuzzing Dictionary Snapshot Player RTL Design CPU Emulator as Proxy Microarchitectural State Quarantine Pool End State Recording Feedback Loop F2XM1 Defect Illegal Instruction Overshoot Defect FCOS Miscomputation Defect Missing x87 Data Pointer Update Defect SiliFuzz: Fuzzing CPUs by Proxy Kostya Serebryany Maxim Lifantsev Konstantin Shtoyk Doug Kwan Peter Hochschild Google LLVMFuzzerTestOneInput XED Integration Unicorn fuzz_emu_x86_64.c Corpus Distillation Register Scrambling
05
third_party/tests/IbexGoogle - third_party/Surelog - Git at Google

Processed 46 entities and 55 relations.

46 ent archive
RISCV-DV SystemVerilog UVM RISC-V RTL RV32IMAFDC RV64IMAFDC CSR privileged mode page table randomization trap and interrupt handling MMU stress test illegal instruction generation HINT instruction generation random branch instruction generation debug mode support instruction generation coverage model co-simulation spike riscv-ovpsim sail-riscv Synopsys VCS Cadence Incisive/Xcelium Mentor Questa riscv-gcc run.py gen_csr_test.py riscv_instr_gen_config.sv riscv_core_setting.sv riscv_instr_cover_group.sv riscv_load_store_instr_lib.sv cov.py directed instruction stream random instruction generation functional coverage handshaking mechanism PMP virtual address translation memory region configuration regression test Google LowRISC IBEX RISC-V core ISS simulation sub-program generation CSR test generation
01
Balancing Scalability and Uniformity in SAT Witness Generator

Processed 30 entities and 55 relations.

30 ent archive
Constrained-Random Verification Uniform Generation of SAT Witnesses UniGen UniWit XORSample' PAWS ApproxMC CryptoMiniSAT Hashing-Based Sampling XOR-based Hash Partitioning Independent Support Almost-Uniform Generator Approximate Model Counting Boolean CNF Formula Markov Chain Monte Carlo Sampling BDD-Based Sampling Simulation-Based Functional Verification RTL Model Test Vector Generation Tseitin Encoding Leapfrogging Heuristic Supratik Chakraborty Kuldeep S. Meel Moshe Y. Vardi Stefano Ermon Carla P. Gomes UniGen Paper (DAC 2014) r-wise Independent Hash Functions SAT Witness sharpSAT
02
An Advanced Constrained Random Verification Environment for SystemC0.5cm

Processed 35 entities and 42 relations.

35 ent archive
Constrained Random Verification SystemC SCV Electronic System Level Design Testbench Automation Random Variable Random Object Constraint Inheritance Dynamic Constraints Constraint Management Inline Generators Parallel Constraint Solving BDD-based Constraint Solving SAT/SMT Solving Portfolio Approach Uniform Distribution ALU Stimulus Generation randv rand_obj rand_vec Generator metaSMT Daniel Große Finn Haedicke Hoang M. Le Rolf Drechsler University of Bremen An Advanced Constrained Random Verification Environment for SystemC Quality-Driven SystemC Design SMT-based stimuli generation in the SystemC verification library Improvements for constraint solving in the SystemC verification library Soft Constraint Hard Constraint References in Constraints Vector Constraints
03
Method and apparatus for verifying integrated circuit design using a constrained random test bench - Oracle America, Inc.

Processed 34 entities and 57 relations.

34 ent archive
Constrained Random Test (CRT) Directed Test Bench Test Vector Design Under Test (DUT) CRT Test Bench SystemVerilog Register Transfer Level (RTL) Instruction Abstraction Layer (IAL) Control Command Bus Macro Instruction (MI) Atomic Instruction (AI) Program Instruction Sequence Interrupt Service Routine (ISR) Instruction Sequence Noise Instruction Constrained Random Verification Order Dependent Instructions Polling Instruction Functional Coverage Program Instruction Streamer Noise Instruction Streamer Interrupt Service Instruction Streamer Custom Instruction Streamer Priority Scheduler Instruction Translator Control Bus Master BFM Module Control Bus Slave BFM Module Test Case Generator Test Manager Register Abstraction Layer (RAL) Verification Methodology Manager (VMM) Integrated Circuit (ASIC) Design Randomized Instruction Sequence Instruction Queue Control Path Verification
01
Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review

Processed 59 entities and 74 relations.

59 ent archive
RISC-V Formal Verification Control Path Verification Symbolic Execution Bounded Model Checking Model Checking Theorem Proving AI-Assisted Verification Parameterised Invariants SMT-based Verification Hybrid Automata Modeling Abstraction Refinement Compositional Reasoning Predicate Abstraction Reinforcement Learning for Proof Generation Non-Interference and Information Flow Analysis RTL Instruction Set Architecture Control and Status Registers Pipelined CPU Finite State Machine Open-Source Hardware System-on-Chip Temporal Logic Coq Isabelle Z3 Yices SymbiYosys Yosys JasperGold Uppaal HyTech SMT Solvers RISC-V Formal: A Framework for Formal Specification and Verification of RISC-V ISA Symbiotic Verification of RISC-V Processors RV-Match: A Formal RISC-V Instruction-Level Semantics Matcher SMT-based Bounded Model Checking for RISC-V Control Logic CSRFormal: Formal Verification of Control and Status Registers in RISC-V AI-Assisted Proof Strategy Selection for RISC-V Formal Verification R2V: A RISC-V to Verilog Translation Framework for Formal Verification Hybrid Automata and Formal Modeling for Safety-Critical RISC-V Control Systems Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification Scalability of Formal Verification in Multi-Core RISC-V Systems Deep Inference of RTL Assertions Using Transformer Models Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review Aparna Mohan North Carolina State University University of California, Berkeley PicoRV32 Rocket Core Ariane Floating-Point Unit Multi-Core RISC-V Systems Secure Boot Verification Neuromorphic and Quantum Control Paths Dynamic Interpolation Framework Assertion Inference from RTL Abstract Interpretation
02
GoldenFuzz Fuzzing Framework

Processed 35 entities and 35 relations.

35 ent archive
GoldenFuzz Golden Reference Model RTL processor verification coverage-guided fuzzing two-stage fuzzing pipeline Spike or1ksim ModelSim Synopsys VCS GPT-2-based instruction generation Direct Preference Optimization SimPO instruction block ISA-level semantic validity branch coverage condition coverage FSM coverage toggle coverage expression coverage RocketChip BOOM CVA6 BA51-H Cascade DifuzzRTL TheHuzz ChatFuzz Cadence JasperGold hardware fuzzing lockstep differential comparison Wu et al. 2025 GoldenFuzz Tyagi et al. 2022 Retrieval-Augmented Generation RISC-V ISA Device Under Test
03
Method and apparatus for generating instruction/data streams employed to verify hardware implementations of integrated circuit designs - Motorola, Inc.

Processed 45 entities and 63 relations.

45 ent archive
instruction/data stream generation hardware implementation verification integrated circuit design RTL model gate level schematic instruction template register model exception and interrupt events boundary condition testing pipeline sequence verification machine state verification intermediate state verification program counter system element behavior code/data thread resource allocation test directive register file entity expected results generation hardware initialization code/data generation entity template library IBM Israel Technical Report 88.290 IBM Israel high level design language Verilog VHDL Mentor Graphics M code pipeline execution unit memory management unit floating point unit arithmetic logic unit cache memory unit user defined rules event behavior rules ADDC instruction instruction class register definition carry bit software interrupt hardware interrupt stimulus generation for CPU verification partial intermediate state verification without re-initialization nearest-value resource allocation for verification instruction/data stream
04
Path-Based System Level Stimuli Generation - Springer Nature

Processed 66 entities and 57 relations.

66 ent archive
System-on-a-chip Verification – Methodology and Techniques Rashinkar, P. Paterson, P. Singh, L. Kluwer Academic Publishers Nuts and Bolts of Core and SoC Verification Albin, K. Top-level Validation of System-on-Chip in Esterel Studio Berry, G. Bouali, A. Dormoy, J. Blanc, L. Esterel Studio The Transaction-Based Verification Methodology Brahme, et al. Cadence Berkeley Labs Transaction-Based Verification Test Program Generation for Functional Verification of PowerPC Processors in IBM Aharon, A. Goodman, D. Levinger, M. Lichtenstein, Y. Malka, Y. Metzger, C. Molcho, M. Shurek, G. Test Program Generation Functional Verification PowerPC IBM Using a constraint satisfaction formulation and solution techniques for random test program generation Bin, E. Emek, R. Ziv, A. Constraint Satisfaction for Random Test Program Generation Genesys Pro: Innovations in Test Program Generation for Functional Processor Verification Genesys Pro Allon, A. Almog, E. Fournier, L. Marcus, E. Rimon, M. Vinov, M. X-Gen: A Random Test-Case Generator for Systems and SoCs X-Gen Jaeger, I. Naveh, Y. Bergman, G. Aloni, G. Katz, Y. Farkash, M. Dozoretz, I. Goldin, A. Practical Approaches to SOC Verification Mosensoson, G. Verisity Constrained Random Test Environment for SoC Verification using VERA Besyakov, V. Shleifman, D. VERA Constrained Random Test Generation SoC Verification The Design and Implementation of a First-Generation CELL Processor CELL Processor Pham, D. Kahle, J.
05
Signoff Checklist - OpenTitan Documentation

Processed 45 entities and 28 relations.

45 ent archive
Development Stage RTL CSR comportability TL-UL interface clock domain crossing reset domain crossing security countermeasure LFSR seed compile-time random netlist constant UVM RAL model scoreboard functional coverage smoke test constrained-random test nightly regression formal property verification X-propagation ROM firmware CPU testplan DV document DIF shadowed register hardened counter FPGA synthesis ASIC synthesis lint flow CDC checking RDC checking ASSERT_KNOWN assertion COI coverage regtool reggen make_new_dif.py OpenTitan lowRISC UVC testbench JTAG access port cip_lib prim_flop_2sync cm_sec_bind top_earlgrey_fpv_cfgs.hjson
01
Encarsia: Evaluating CPU Fuzzers via Automatic Bug ...

Processed 46 entities and 56 relations.

46 ent archive
ENCARSIA DifuzzRTL ProcessorFuzz Cascade RFUZZ TheHuzz DirectFuzz MorFuzz Yosys JasperGold EnCorpus Hardware Fuzzing Bug Injection Signal Mix-ups Broken Conditionals Multiplexer Tree Intermediate Representation RTL Formal Verification Miter Circuit Coverage Metric Control Register Coverage Multiplexer Select Coverage ISA Simulator SystemVerilog Assertions Assume-Guarantee Reasoning Seed Programs Hardware Description Language RTLIL Instruction Set Architecture RISC-V Design Under Test Netlist Transformation Pull Request Instruction Mutation Ibex CVA6 Rocket BOOM Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection Matej Bölcskei Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich HACK@DAC Competition
01
Performance of a SystemVerilog Sudoku Solver with VCS

Processed 26 entities and 46 relations.

26 ent archive
VCS MathSAT5 Yices Z3 Constrained Random Verification Constraint Solver Conjunctive Normal Form (CNF) SAT Solving Satisfiability Modulo Theories (SMT) Sudoku Constraint Solving Object-Oriented Constraint Composition (OOP) Flat Constraint Composition (FLAT) Clausal Reduction Optimization Latin Square SystemVerilog Sudoku Solver SystemVerilog Test Bench SMT2 Constraint Language Input Perl Jeremy Ridgeway Avago Technologies Synopsys Parasitic Literals Implication Operator in Constraints If-Else Constraint Construct Constant vs Variable in Constraint Performance of a SystemVerilog Sudoku Solver with VCS
04
AI based SystemVerilog TB generation

Processed 55 entities and 95 relations.

55 ent archive
Functional Verification ASIC Design SystemVerilog Testbench Universal Verification Methodology (UVM) Coverage-Directed Generation (CDG) Stimulus Generation Constraint-Based Random Test Generation RTL (Register Transfer Level) Genetic Algorithm (GA) Cell-Based Genetic Algorithm (CGA) Feedback-Adjusted Markov Model Recurrent Neural Network (RNN) Bayesian Network Reinforcement Learning (RL) Graph Neural Network (GNN) Static Code Analysis Natural Language Processing (NLP) Constraint Logic Programming (CLP) Biased-Random Simulation Pseudo-Random Generator (PRG) Constraint Optimization Hierarchical Learning Explainable AI (XAI) Formal Verification Transfer Learning StressTest Unified Coverage Database (UCDB) Coverage Closure Microprocessor Verification Device Under Verification (DUV) State Space Explosion Reward Shaping Assertion Coverage Abstract State Machine (ASM) 8051 Soft Core Processor Bhavin Shah Wagner, Ilya Fajcik, Martin Fine, S. Ziv, A. Goloubeva, O. Samarah, et al. Habibi, Ali Tahar, Sofiène Zeng, Z. AI based SystemVerilog TB generation Microprocessor Verification via Feedback-Adjusted Markov Models Automation of Processor Verification Using Recurrent Neural Networks Automation and Optimization of Coverage-driven Verification A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage Automatic Generation of Validation Stimuli for Application-Specific Processors Design and Verification of SystemC Transaction-Level Models Coverage Directed Test Generation for Functional Verification Using Bayesian Networks Techvulcan Inc IEEE Zeng, Z.
01
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor

Processed 55 entities and 65 relations.

55 ent archive
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor Idris O. Somoye Jim Plusquellic Tom J. Mannos Brian Dziki University of New Mexico Sandia National Laboratories Department of Defense Periodic Built-In-Self-Test information leakage fault fault detection severe fault fault propagation latency Automatic Test Pattern Generation counter-based node monitoring Fault Trigger Binary Executable Fault-Run-Cycle-Based FTBE ATPG-Based FTBE processor state replication Incremental Fault-Triggered Cycle Binary Search Fault-Detected Cycle fault injection scan chain stuck-at fault delay fault inversion fault TopCounters Fault Injection Manager Fault Emulation Engine Emulation ROM Side Loading PODEM Yosys Fault (open-source DFT toolchain) Synopsys Design Compiler RISC-V online assembler SystemVerilog testbench RISC-V RV32I Potato RISC-V processor Advanced Encryption Standard Self-Assertion-Based Countermeasures Dynamic Implementation Verification Architecture Access-Control Extension RTL Design for Testability FPGA emulation Xilinx UltraScale+ MPSoC ZCU102 Wishbone bus binary program ASAP7 standard cell library osu035 standard cell library Coremark benchmark Fault-Run-Cycle-Based FTBE ATPG-Based FTBE Fault Trigger Binary Executable
02
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection

Processed 44 entities and 59 relations.

44 ent archive
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection Matej Bölcskei Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich ENCARSIA hardware fuzzing bug injection signal mix-up broken conditional RTL RISC-V DifuzzRTL ProcessorFuzz Cascade Ibex CVA6 Rocket BOOM Yosys RTLIL multiplexer tree formal verification JasperGold coverage metric ISA simulator differential fuzzing EnCorpus SystemVerilog Assertions assume-guarantee reasoning seed program RFUZZ control register coverage multiplexer select coverage ISA coverage intermediate representation HDL design under test manual bug insertion HACK@DAC competition mutation-based fuzzing false positive elimination ENCARSIA
03
Improvements for Constraint Solving in the SystemC Verification Library

Processed 26 entities and 33 relations.

26 ent archive
SystemC Verification Library SystemC Constraint-based Randomization Random Pattern Simulation Directed Simulation Binary Decision Diagram Uniform Distribution of Constraint Solutions Bit Operators in SCV Constraints BDD Weighting Algorithm Constraint Solver Simulation-based Verification Functional Coverage CUDD scv_constraint_base scv_expression scv_smart_ptr scv_constraint_manager Daniel Große Rudiger Ebendt Rolf Drechsler University of Bremen German Aerospace Center Improvements for Constraint Solving in the SystemC Verification Library Complement Edges in BDD Transaction Recording Data Introspection
04
Contradiction Analysis for Constraint-based Random Simulation

Processed 33 entities and 48 relations.

33 ent archive
Constraint-based Random Simulation Contradiction Analysis Stimulus Generation Directed Simulation Constraint Solving Binary Decision Diagrams Existential Quantification Unsat Core Computation Formal Verification Design Verification SCV Library CUDD BDD Package SystemC SystemVerilog Over-constraining Corner Case Test Scenarios Constraint Contradiction Minimal Unsatisfiable Subformula Boolean Satisfiability System-on-Chip PCIe Transaction Generator Bus Functional Model Random Constraint Verification SCV_CONSTRAINT Macro ContradictionAnalysis Algorithm Daniel Große Robert Wille Robert Siegmund Rolf Drechsler University of Bremen AMD Saxony LLC Contradiction Analysis for Constraint-based Random Simulation Design Verification
01
https://arxiv.org/pdf/2603.25354

Processed 66 entities and 73 relations.

66 ent archive
Fuzzing Coverage-based Greybox Fuzzing Greybox Fuzzing Whitebox Fuzzing Blackbox Fuzzing Mutation-based Fuzzing Generation-based Fuzzing Snapshot-based Fuzzing Multi-target Coverage-based Greybox Fuzzing Code Coverage Measurement Symbolic Execution Basic Block Coverage Tracing TCG-based Instrumentation Address-based Coverage Filtering VM Snapshot Save and Restore Power Scheduling Binary Search for Address Filtering MTCFuzz QEMU AFL++ libFuzzer syzkaller ItyFuzz KCOV Ghidra addr2line bpftrace GCC LLVM Code Coverage Basic Block Seed Corpus Tiny Code Generator QMP Protocol ELF Binary Format Shared Memory Coverage Map TrustZone Trusted Execution Environment Memory Address Isolation IsInteresting Function AssignEnergy Function Test Harness qcow2 Snapshot Storage Sanitizer Coverage Instrumentation Vulnerability Discovery CVE-2025-40031 OpenSBI OP-TEE RISC-V Architecture ARM Architecture Linux Kernel Firmware Trusted Firmware-A Multi-target Coverage Feedback Coverage Visualization Fuzzing Workflow Masami Ichikawa Kuniyasu Suzaki Institute of Information Security Multi-target Coverage-based Greybox Fuzzing (Master's Thesis 2025) mtcfuzz_record_tb_exec analyze_coverage mtcfuzz-trace-start QMP command mtcfuzz-trace-stop QMP command afl-fuzz.c save_if_interesting afl-fuzz.c has_new_bits
02
Stimuli Generation

Processed 37 entities and 49 relations.

37 ent archive
COMS30026 Design Verification: Stimuli Generation Kerstin Eder Avi Ziv IBM Research Labs Haifa University of Bristol Stimuli Generation Verification Plan Test Scenarios Matrix PowerPC Processor RISC Architecture Pipeline Forwarding Mechanism Instruction Pair Coverage Distributed Generators Single Unified Generator Synchronized Generators Level of Abstraction Bit-Level Abstraction Sequence-Level Abstraction Command and Data Instruction Level Algorithmic Level Abstraction Error Injection Offline Test Generation Online Test Generation Out-of-Order Instruction Generation Static Test Generation Dynamic Test Generation Reference Model Test Length Constrained Pseudo-Random Stimulus Generation Corner Case Coverage Design Under Verification Dispatch Queue Instruction Fetch Instruction Cache Data Cache Processor Verification Environment
03
HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

Processed 39 entities and 46 relations.

39 ent archive
Integrated Circuit Verification Universal Verification Methodology HAVEN Large Language Model Hardware Description Language SystemVerilog UVM Testbench UVM Sequence Protocol-Aware Sequence Domain-Specific Language Jinja2 Template Engine Rule-Based Code Generation UVM Blueprint Protocol Flows Bus Functional Model Coverage Gap Report Device Under Test AXI4-Lite Protocol Wishbone Protocol Direct Interface Protocol Bus-Handshake Timing Functional Coverage Code Coverage Constrained Random Stimulus LLM Agent AutoBench CorrectBench ConfiBench UVM2 RTL UVM Driver UVM Monitor UVM Scoreboard Structured JSON Artifact Field Value Sweep Toggle Pattern FIFO Stress Test Register Write Step Poll Step Compile-Fix Loop
04
[PDF] Processor Verification using Symbolic Execution - AGRA | Uni Bremen

Processed 37 entities and 50 relations.

37 ent archive
Symbolic Execution KLEE Co-Simulation Instruction Set Simulator (ISS) RTL RISC-V MicroRV32 RISC-V VP Verilator Fuzzing Constrained Random Instruction Generation Model-Based Test Generation Symbolic Instruction Memory Symbolic Data Memory Sliced Symbolic Registers Symbolic Execution Interface Voter (Mismatch Detection) RISC-V Formal Interface (RVFI) riscv-formal Bounded Model Checking (BMC) Instruction Stream SpinalHDL LLVM Coverage-Guided Fuzzing Control and Status Registers (CSRs) Error Injection VexRiscV PicoRV32 RISCV-DV Niklas Bruns Vladimir Herdt Rolf Drechsler University of Bremen DFKI GmbH Processor Verification using Symbolic Execution: A RISC-V Case-Study Processor Verification Instruction Set Architecture (ISA)
05
[PDF] CV32E40P updates: customizing an open-source RISC-V core at ...

Processed 28 entities and 25 relations.

28 ent archive
stimulus generation pseudo-random test-program generation RISCV-DV COREV-DV manually generated C and Assembly programs Coremark Embench IOT test suite bus cycle delay randomization UVM Agent Open Bus step&compare ImperasDV reference model instruction set simulator Core-V-Verif RISC-V Verification Interface Universal Verification Methodology Formal Verification Siemens EDA Onespin RISC-V ISA app CV32E40P RV32Xpulp ISA extension OpenHW Group Dolphin Design Google Imperas Software Embecosm CV32E40P updates: customizing an open-source RISC-V core at industrial-grade
06
TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

Processed 59 entities and 91 relations.

59 ent archive
TaPaFuzz Fuzz Testing Graybox Fuzzing Control Flow Coverage Coverage Map Basic Block Coverage Control Flow Edge Coverage Corpus Input Mutation Blackbox Fuzzing Whitebox Fuzzing FPGA Hardware Acceleration ISA Emulation AXI Bus Protocol Fuzzer Result Aggregation Cache Invalidation Branch Predictor Persistent Mode Forkserver Hash-Based Indexing Processing Element Partial Design Reset Dynamic Binary Translation Compiler Instrumentation Hardware-Based Control Flow Tracing AFL++ LibAFL LibFuzzer QEMU TaPaSCo Xilinx Vivado CVA5 RISC-V Core AXI Reset Wrapper Fuzzer Result Aggregation Hardware libtapasco ArduinoJson RISC-V ISA IoT Firmware Soft-Core Processor Scratchpad Memory Memory-Mapped IO PCIe Interface Florian Meisel David Volz Christoph Spang Dat Tran Andreas Koch Andrea Fioraldi Dominik Maier Michal Zalewski Technical University of Darmstadt Embedded Systems and Applications Group TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing AFL++: Combining Incremental Steps of Fuzzing Research The TaPaSCo Open-Source Toolflow DDR4 Memory Interrupt Request System-on-Chip Hardware-Based Control Flow Tracing
01
[PDF] HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient ...

Processed 36 entities and 39 relations.

36 ent archive
HWFuzz RISC-V processor verification fuzzing coverage-directed generation RISC-V instruction sequence generation FPGA acceleration hardware fuzzer IP mutation-based fuzzing random instruction generation stimuli packing stimuli constraints instruction injector coverage corpus synthesizable coverpoints differential checking ENCORE Rocket Core design-under-test (DUT) RTL design RFUZZ DifuzzRTL TheHuzz Cascade American Fuzzy Lop (AFL) libfuzzer RV64I extension RV64G extension Zynq UltraScale+ Yang Zhong Haoran Wu Yungang Bao Kan Shi Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences University of Cambridge HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
02
©Copyright 2023 Anoop Mysore Nataraja

Processed 65 entities and 71 relations.

65 ent archive
ZP Cosim Zynq-Parrot Dromajo Surelog Universal Hardware Data Model Verilator Synopsys VCS Synopsys Zebu Server 5 Cadence Palladium Z1/Z2 AFL++ FuzzFactory Synopsys VC Formal RISC-V Proxy Kernel RISCV-DV BaseJump STL Chisel TL-Verilog Bluespec FPGA-accelerated cosimulation automated coverage instrumentation Mux Toggle Coverage coverage metric hardware fuzzing cosimulation golden reference model program generator test vector mutation coverpoint unreachability analysis coverage aliasing localized cross products structural coverage functional coverage formal verification case-statement coverage toggle-only coverage coverspace preprocessing hardware state-space ISA-level coverage microarchitectural coverage FSM coverage agile chip design randomized test vectors FPGA emulation FPGA shell SAT solver Reinforcement Learning for hardware fuzzing RISC-V processor verification BlackParrot Ultra96v2 Coverage Walker VPI API SystemVerilog RTL simulation Anoop Mysore Nataraja Michael Taylor University of Washington Bespoke Silicon Group Air Force Research Laboratory DARPA SPEC 2017 benchmarks BEEBS benchmarks RISC-V Tests Zynq Farm AXI interface
03
Design Verification - OpenTitan Documentation

Processed 39 entities and 25 relations.

39 ent archive
SV/UVM Testbench Dynamic Simulation Formal Property Verification (FPV) SVA Testbench TileLink Protocol Compliance Verification PWRMGR IP CIP Testbench Architecture pwrmgr_env_pkg tb.sv pwrmgr.sv tl_agent ralgen regtool RAL Model pwrmgr_base_vseq pwrmgr_smoke_vseq pwrmgr_wakeup_vseq pwrmgr_aborted_low_power_vseq pwrmgr_reset_vseq pwrmgr_wakeup_reset_vseq pwrmgr_lowpower_wakeup_race_vseq Functional Coverage Model Constrained Random Stimulus Slow Responder Task Fast Responder Task Clock Domain Crossing (CDC) Slow FSM Fast FSM pwrmgr_clock_enables_sva_if pwrmgr_ast_sva_if Low Power Entry/Exit Wakeup Sources Reset Request Handling pwrmgr_bind.sv tlul_assert clkmgr_pwrmgr_sva_if dvsim lowRISC OpenTitan
05
Difftest and Co-Simulation | OpenXiangShan/XiangShan | DeepWiki

Processed 27 entities and 29 relations.

27 ent archive
Difftest Co-Simulation NEMU Spike Verilator VCS Fork-Based Fast Checkpointing LightSSS Profile-Guided Optimization Design Under Test Golden Reference Model Architectural State RISC-V RTL XiangShan scripts/xiangshan.py SimTop.sv difftest-interface.sv NUMA-Aware Core Allocation Cache Coherence SPEC CPU 2006 CoreMark RV64GCBV numactl Multi-Core Validation XSNoCDiffTopConfig Multi-Core Validation
06
https://lirias.kuleuven.be/retrieve/100718

Processed 40 entities and 57 relations.

40 ent archive
Towards a framework for constraint-based test case generation François Degrave Tom Schrijvers Wim Vanhoof Katholieke Universiteit Leuven University of Namur constraint-based test case generation constraint programming symbolic execution whitebox testing structural coverage CP search strategies depth-bounded search branch-and-bound optimization random test data generation constraint propagation Constraint Handling Rules MC/DC coverage execution path control-flow graph heap-allocated data structures pointer-based data structures cons cell cyclic data structures coverage criterion regression testing test suite non-determinism in constraint solving Herbrand equality program state constraint variable ImpL imperative language SWI-Prolog prototype Graphviz ATGen Monadic Constraint Programming framework Automatic generation of test inputs for Mercury Monadic Constraint Programming Mercury logic programming language Spark ADA
04
RISC-V Lockstep Co-Simulation: Retirement-Level Step-and-Compare for Faster Verification & Debug | by Alpinum Consulting | Medium

Processed 39 entities and 45 relations.

39 ent archive
Lockstep Co-Simulation Retirement-Level Step-and-Compare Instruction Retirement Architectural State Asynchronous Events Constrained-Random Instruction Streams Directed ISA Tests Configurable State Mask Weak Memory Model Virtual Memory Operations CSR Side Effects RTL Simulation Reference Model Lockstep Co-Simulation Methodology Checkpoint-Based Regression Mismatch Reporting at Point of Failure Non-Deterministic Source Masking Seed-Based Deterministic Replay RVVI ImperasDV ImperasFPM Synopsys VCS Verdi UVM SystemVerilog RISC-V RTL General-Purpose Registers Control and Status Registers Program Counter Synopsys Imperas S. Davidmann Understanding the RISC-V Verification Ecosystem RISC-V Processor Verification Requires the Full Toolbox Co-Simulation Harness Scoreboard Functional Coverage Multi-Hart Design
05
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core

Processed 49 entities and 52 relations.

49 ent archive
Single Event Upset Soft Error Silent Data Corruption Formal Verification Model Checking Bounded Model Checking Fault Injection Simulation-Based Fault Injection Backward Tracing Forward Tracing Cone-Of-Influence Analysis State Space Explosion Memory Abstraction Strobe Properties Architectural Properties Crash Properties Hang Properties Triple Modular Redundancy Register Transfer Level XOR-Gate Fault Injection Fault Controller Module Misaligned Instructions Random Fault Injection Fault Coverage SystemVerilog Assertions Cadence JasperGold FPV JasperGold Superlint App SystemVerilog Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core Bing Xue Mark Zwolinski University of Southampton lowRISC RISC-V Ibex Core RV32IMC Instruction Set Control Status Registers Physical Memory Protection Finite State Machine Program Counter Register File Instruction FIFO ISO 26262 Fault Tree Analysis Runtime Verification AUX SystemVerilog Code Liveness Properties Safety Properties Double Event Upset
06
HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

Processed 69 entities and 81 relations.

69 ent archive
HiFuzz Hierarchical Reinforcement Learning Hardware Fuzzing Mutation-Based Fuzzing Constructive Test Generation Coverage-Guided Fuzzing Program Agent Basic Block Agent Semantic-Aware Basic Block Encoder Adaptive Coverage Reward Mechanism Intrinsic Novelty Reward Reward Sparsity Rainbow DQN Proximal Policy Optimization Random Network Distillation Masked Language Modeling Contrastive Learning Upper Confidence Bound Multi-Armed Bandit Bi-LSTM Structured RISC-V Tokenizer Basic Block Similarity Metric Constrained Random Verification Formal Verification Differential Testing RFUZZ DifuzzRTL ProcessorFuzz Cascade ChatFuzz GenHuzz Verilator Spike Cocotb Encarsia RISC-V RTL MUX Coverage Control Register Coverage Line Coverage Toggle Coverage Chisel ISA Pre-Simulation Basic Block Hierarchical Configuration Dual-Advantage Actor Loss Speculative Execution Vulnerabilities Meltdown Spectre Moore's Law GPT-2 RWKV Curriculum Learning Online Cluster-Distance Novelty Estimator Module-Level Coverage Weighting Multi-Head Actor-Critic HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing Ya Wang Hanwei Fan Zhenguo Liu Xiaofeng Zhou Yangdi Lyu Jiang Xu Wei Zhang Rocket Core BOOM Core CVA6 Structured RISC-V Tokenizer Bi-LSTM
02
METHOD AND APPARATUS FOR A CONSTRAINED RANDOM TEST BENCH - Patent application

Processed 29 entities and 41 relations.

29 ent archive
Constrained Random Test (CRT) Instruction Abstraction Layer (IAL) Instruction Streamer Priority Scheduler Instruction Translator Program Instruction Streamer Noise Instruction Streamer Interrupt Service Instruction Streamer Custom Instruction Streamer Macro Instruction (MI) Atomic Instruction (AI) Order Dependent Instruction Test Case Generator (TCG) Test Manager (TM) Control Bus Master Bus Functional Model (BFM) Register Abstraction Layer (RAL) Control Command Bus Design Under Test (DUT) Interrupt Service Routine (ISR) Instruction Sequence Directed Test Bench Constrained Random Verification SystemVerilog RTL (Register Transfer Level) VMM (Verification Methodology Manual) Sun Microsystems, Inc. Polling Instruction Functional Coverage Instruction Queue ASIC (Application Specific Integrated Circuit)
03
[PDF] Threadmill: a post-silicon exerciser for multi-threaded processors

Processed 49 entities and 54 relations.

49 ent archive
Threadmill Post-Silicon Validation Bare-Metal Execution On-Platform Test Generation Pseudo-Random Test Generation Multi-Pass Consistency Checking Static Branch Generation Dual-Pass Branch Generation Off-Platform Floating-Point Operand Pre-Generation Joint Random Seed for Distributed Generation Concurrent Multi-Threaded Test-Case Generation Joint Random Collision Generation Illegal Instruction Interrupt Handler for Branch Completion Test Template Stimuli Generation Functional Verification Hardware Acceleration Platform Floating-Point Unit Verification Memory Coherence Testing Coverage Model Architectural Model Reference Model Constraint Satisfaction Problem Genesys-Pro FPgen Multi-Threaded Processor Testing Verification Plan Exerciser Image Builder Silicon Bring-Up Tape-Out Random Test Program Generation Write-Write Collision Load/Store Instruction Generation Shared Memory Multiprocessor Assertion Testing Threadmill: A Post-Silicon Exerciser for Multi-Threaded Processors Allon Adir Maxim Golubev Shimon Landa Amir Nahir Gil Shurek Vitali Sokhin Avi Ziv IBM Research - Haifa POWER7 Observability in Post-Silicon Platforms Pre-Silicon Verification Unified Pre- and Post-Silicon Verification Methodology Memory Trace for Debug Address Translation Path Generation
04
Towards Automating Simulation-Based Design Verification Using ILP

Processed 55 entities and 49 relations.

55 ent archive
Genesys-Pro Genesys-Pro: Innovations in test program generation for functional processor verification Adir, A. Almog, E. Fournier, L. Marcus, E. Rimon, M. Vinov, M. Ziv, A. test program generation functional processor verification Writing Testbenches: Functional Verification of HDL Models Bergeron, J. biased random instruction generation genetic approach to automatic bias generation Bose, M. Shin, J. Rudnick, E.M. Dukes, T. Abadir, M. coverage directed test generation Bayesian network based coverage directed test generation Braun, M. Fine, S. evolutionary test program generation microprocessor design verification Corno, F. Cumani, G. Reorda, M.S. Squillero, G. Automatic Test Program Generation: A Case Study Coverage directed test generation for functional verification using Bayesian networks functional coverage Hole analysis for functional coverage data Lachish, O. Ur, S. Inductive Logic Programming Progol Muggleton, S. Cost evaluation of coverage directed test generation for the IBM mainframe Nativ, G. Mittermaier, S. IBM formal verification Microprocessor design verification by two-phase evolution of variable length tests Smith, J. Bartley, M. Fogarty, T. two-phase evolution of variable length tests A Genetic Testing Framework for Digital Integrated Circuits Yu, X. Fin, A. Fummi, F. automatic test generation RTL verification
05
Automatic identification of information useful for generation-based ...

Processed 39 entities and 40 relations.

39 ent archive
Functional Verification Stimulus Generation Design Under Test (DUT) Architectural Knowledge Micro Architectural Knowledge Design Knowledge Test Template Instruction Generator Constraint Satisfaction Problem (CSP) Simulation-Based Verification Reference Model HDL Simulator Effect Determinator Machine Learning Classification Decision Tree Learning ID3 Algorithm C4.5 Algorithm Instruction Attributes Data Collector Data Classifier Performance Metrics Generation Failure Classification DUT Definition Design Knowledge Definer Pipeline Cache Genesys-Pro IBM Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification A. Adir Verification Apparatus Hardware Description Language (HDL) Branch Conditional (bc) Instruction Condition Register (CR) Test Program Generation Instruction Opcode Register Exception Behavior CPU Utilization
01
Constraint satisfaction for test program generation

Processed 17 entities and 23 relations.

17 ent archive
Model-Based Test-Generator Constraint Satisfaction Automatic Test Program Generation Memory Access Generation Address Constraint Satisfaction Addressing Modes Complex Addressing Modes PowerPC Architecture x86 Architecture Constraint satisfaction for test program generation Daniel R. Lewin Laurent Sébastien Fournier Moshe Levinger E. Roytman Gil Shurek IBM Research - Haifa Constraint-Based Automatic Test Data Generation
02
US7627843B2 - Dynamically interleaving randomly generated test ...

Processed 54 entities and 56 relations.

54 ent archive
functional verification dynamic verification random test generation test template dynamic interleaving of test templates combined test case design-under-verification coverage criteria transaction sparseness unbreakable section baseline template weighted template selection cache operations direct memory access CPU-initiated memory access prologue section epilogue section global knowledge base inter-scenario event address collision multiprocessor verification test generator template arbitrator unit execution engine design verification system constraint satisfaction for test program generation model-based test generation user-defined coverage on-the-fly test generation stimulus injection User Defined Coverage—A Tool Supported Methodology for Design Verification Model-Based Test Generation For Processor Design Verification Constraint Satisfaction for Test Program Generation Test Program Generation for Functional Verification of PowerPC Processors in IBM Adaptive Test Program Generation (US 2003/0130813 A1) Raanan Grinwald Eran Harel Michael Orgad Shmuel Ur Avi Ziv Y. Lichtenstein Y. Malka A. Aharon L. Fournier D. Lewin M. Levinger E. Roytman Gil Shurek GenerateSingleTransaction pseudocode WeightedChoice pseudocode CPU processor simulation RTL
01
Test-driven Generation of Constraint Satisfaction Problems Using Large Language Models

Processed 38 entities and 41 relations.

38 ent archive
Constraint Satisfaction Problem Large Language Model Test-Driven Development Knowledge Acquisition Knowledge Base Generation Constraint Model Iterative Prompt Feedback Loop Semantic Validation One-Shot Learning Traveling Salesman Problem N-Queens Problem Magic Square Problem Map Coloring Problem Syntactic Validation Chain of Thought Prompting Program of Thoughts PyChoco Choco Solver ChatGPT ChatGPT-4.1 GitHub Copilot LangChain GPT-Engineer SATzilla Protégé MCP-Solver Model Context Protocol ReAct verify_solutions method run_loop function TSP constraint model (LLM-generated) Test-Driven Generation of CSPs Using LLMs Christian Bähnisch Lothar Hotz Alexander Felfernig Sebastian Lubos Hamburger Informatik Technologie-Center Graz University of Technology
02
catnap: Generating Test Suites of Constrained Combinatorial Testing with Answer Set Programming

Processed 28 entities and 36 relations.

28 ent archive
catnap Constrained Combinatorial Testing Answer Set Programming clingo CASA TCA ACTS Cascade Covering Array Constrained Mixed Covering Array Combinatorial Testing test suite generation soft constraints multi-criteria optimization prioritized combinatorial testing Constraint Answer Set Programming event-sequence testing Mutsunori Banbara Katsumi Inoue Torsten Schaub Naoyuki Tamura Kobe University NII catnap: Generating Test Suites of Constrained Combinatorial Testing with Answer Set Programming ASP encoding for strength-2 CMCA finding ASP encoding for optimal strength-2 CMCA finding ASP encoding for strength-2 CCT solving with weak coverage constraints gringo
04
Hardware accelerated constrained random test generation

Processed 48 entities and 68 relations.

48 ent archive
Hardware accelerated constrained random test generation B. Pal A. Sinha P. Dasgupta P.P. Chakrabarti K. De Indian Institute of Technology Kharagpur Synopsys India constrained random test generation hardware accelerated simulation coverage-driven randomised verification constrained random value selection layered test bench architecture entailed regions constraint pre-processing strip computation overlapping constraint set strip weight integer linear programming linear feedback shift register pseudo-random number generation bound refinement bi-variate linear constraints solution space projection inequality constraint splitting Bus Functional Model field programmable gate array two-step constrained random synthesis GenRandNum procedure RefineBound procedure ReCompTotWt procedure GenerateSolution algorithm ComputeStrip algorithm constraint backtracking search SystemVerilog OpenVera Specman-Elite ILOG CPLEX Synopsys Design Compiler Reference Verification Methodology Verification Methodology ARM AMBA AHB IBM CoreConnect PCI Bus convex polygon solution region constrained random test bench for ARM AMBA constrained random test bench for IBM CoreConnect design-under-test
05
New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores

Processed 35 entities and 36 relations.

35 ent archive
μGP Evolutionary Algorithm Test Program Generation Pseudo-Random Test Generation Feedback-Based Test Generation Hardware Acceleration Tournament Selection Self-Adaptation Local Mutation Operator Individual Aging Elite Population Selection Fault Simulation FPGA-Based Hardware Emulation Stuck-At Fault Coverage Assembly Program Generation Pipeline Testability Functional Test Post-Production Test Turing-Complete Program Fitness Function Elitism CPU Microprocessor Core SPARCv8 Virtex 2000E FPGA Politecnico di Torino E. Sanchez M. Schillaci M. Sonza Reorda G. Squillero L. Sterpone M. Violante VHDL Model Netlist Functional Built-In Self Test MicroGP — An Evolutionary Assembly Program Generator Fully Automatic Test Program Generation for Microprocessor Cores
06
http://costa.fdi.ucm.es/papers/costa/RojasG-Z12.pdf

Processed 36 entities and 44 relations.

36 ent archive
A Framework for Guided Test Case Generation in Constraint Logic Programming José Miguel Rojas Miguel Gómez-Zamalloa Technical University of Madrid Complutense University of Madrid Symbolic Execution Test Case Generation Guided Test Case Generation Constraint Logic Programming Path Explosion Problem Trace Abstraction Coverage Criterion All-Local-Paths Coverage Criterion Program-Points Coverage Criterion Trace-Guided TCG Selective Testing Unit Testing CLP-Translated Program Trace Term Termination Criterion Partial Evaluation Program Slicing Trace-Abstraction Refinement Instantiation Mode Analysis Predicate Abstraction Loop-K Termination Criterion Dynamic Memory Allocation PET jPET guidedTCG Prolog Implementation net.datastructures library Structural Coverage Criteria Control Flow Graph Trace Generator Java Bytecode Fixpoint Computation
01
[PDF] Verification Of Risc-V Core Blocks Using Uvm - RJ Wave

Processed 48 entities and 50 relations.

48 ent archive
RISC-V UVM SystemVerilog Constrained-Random Stimulus Generation Coverage-Driven Verification Directed Testing Assertion-Based Verification Functional Coverage UVM Sequence UVM Sequencer UVM Driver UVM Monitor UVM Scoreboard UVM Coverage Collector Instruction Fetch Unit Instruction Decode Unit ALU Load-Store Unit Register File Control and Status Registers Pipeline and Hazard Unit Interrupt and Exception Unit Branch Prediction Unit Spike ISA Simulator RISCV-DV ModelSim QuestaSim VCS Visual Studio Code Reference Model RTL System on Chip TLM Co-Simulation Regression Testing SystemVerilog Assertions Integrated UVM-TLM Co-Simulation for RISC-V Verification Survey of Verification of RISC-V Processors UVM Verification of RISC-V Instruction Set RISC-V UVM Verification Thesis System-Level Verification of Multi-Core RISC-V CORE-V-VERIF OpenHW Group Nithyashree S Monisha J K M G Jatin Dr. Ambedkar Institute of Technology UVM Agent Random Instruction Generator
03
[PDF] RISC-V Core & SoC Verification

Processed 44 entities and 44 relations.

44 ent archive
RISC-V Instruction Set Architecture Automated Test Generation Constrained Random Verification AI Planning Algorithm Synthesis Test Suite Synthesis Custom Instruction Verification Compliance Assurance Core Integrity Verification SoC Integrity Verification Concurrent Test Execution Page Based Virtual Memory Testing Memory Management Unit Cache Coherency MOESI Cache States Atomic Operations Testing Dekker Memory Ordering False-Share Memory Stress Testing Architectural Compliance Testing Firmware-First Testing Power Management Verification Security Verification Performance-Power Profiling End-to-End Use Case Testing Multi-Core Verification Test Graph AXI Wrap Transactions Coherent Mesh Network DDR Memory Model Verification Breker SystemVIP Library Core Integrity FastApps RISC-V System Integrity TrekApp ARM System Integrity TrekApp Cache Coherency TrekApp 2.0 Firmware-First TrekApp Power Management TrekApp Security TrekApp Networking TrekApp Breker Verification Systems RISC-V International Adnan Hamid trek_microloop_write_check8 RV64 Architecture Single Core Multi-Thread Testing
04
[PDF] Security-Aware Benchmarks for Performance Exploration of CHERI ...

Processed 28 entities and 44 relations.

28 ent archive
TestRIG CHERI RISC-V Constrained Random Instruction Generation Security-Aware Instruction Stream Post-Processing Direct Instruction Injection RISC-V Formal Interface Sail RISC-V Formal Model Virtual Prototype In-Memory Computing Capability-Based Memory Protection Tagged Memory RTL Simulation CHERI Early Benchmarks RISC-V VP Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures Spandan Das Sayak Deb Khushboo Qayyum Sallar Ahmadi-Pour Christoph Luth Rolf Drechsler University of Bremen DFKI Benchmark Suite Design Space Exploration Memory Safety Instruction Stream Generation
05
μCFI: Formal Verification of Microarchitectural Control-flow Integrity

Processed 60 entities and 61 relations.

60 ent archive
μCFI: Formal Verification of Microarchitectural Control-flow Integrity Katharina Ceesay-Seitz Flavien Solt Kaveh Razavi ETH Zurich Microarchitectural Control-Flow Integrity (μCFI) Constant-Time (CT) execution Control-Flow Integrity (CFI) Register Transfer Level (RTL) Information Flow Tracking (IFT) Formal Property Verification (FPV) taint tracking Program Counter (PC) Instruction Under Verification (IUV) microarchitectural control flow (μCF) declassification of legal flows Instruction Operand Constraint (IOC) taint injection hardware fuzzing timing side-channel attack data-independent execution latency logic abstraction model checking non-influencing (ni) instructions control-influencing (ci) instructions value-influencing (vi) instructions forwarding paths RISC-V ISA pipeline CPU architecture General-Purpose Register (GPR) Control and Status Register (CSR) instruction word (IW) CellIFT CellDFT Jasper FPV Yosys Cascade CPU fuzzer SystemVerilog Assertions (SVA) precise taint injection data flow tracking (DFT) cell-level taint instrumentation static design analysis logic gate shadow logic instrumentation (GLIFT) RTLIFT μCFI verification toolchain Kronos RISC-V CPU PicoRV32 RISC-V CPU Ibex RISC-V CPU Scarv RISC-V CPU unbounded instruction sequence verification hardware security vulnerability CVE (Common Vulnerabilities and Exposures) control-flow hijack delay injection attack formal verification register file instruction operand shadow logic multiplexer select signal RISC-V Data-Independent Execution Latency (DIEL) mode
06
µArchiFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections

Processed 72 entities and 94 relations.

72 ent archive
μARCHIFI Yosys Fault Injection Microarchitectural Fault Model Faulty Transition System Hardware Transition System Bounded Model Checking Attacker Model Sandboxing Concretization RTL RTLIL Reachability Property SW/HW Co-verification Program Counter Bit-flip Fault Effect Equivalence Checking Formal Verification Prefetch Buffer Pipeline Forwarding Mechanism Synchronous Digital Circuit AIGER SMV BTOR2 SMT-LIB Differential Fault Analysis SystemVerilog Assertion VCD Waveform Trace AES Key Schedule Clock Glitch Electromagnetic Pulse Laser Fault Injection PONO BTORMC YOSYS-BMC FIVER SYNFI VerFI Lazart ARMORY Cadence JasperGold Synopsys VC Formal Siemens QuestaVerify nuXmv SimpliFI SAMVA FaultRTLIL μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections Simon Tollec Mihail Asavoae Damien Couroussé Karine Heydemann Mathieu Jan CEA List Thales DIS OpenHW Group LowRISC RISC-V CV32E40P Ibex VerifyPIN FISSC Benchmark RV32IMC Verilog Binary Program Lockstep Core Tiny AES SMT Solver Combinational Function Register Transition Function Model Checking
01
Hardware Support to Improve Fuzzing Performance and Precision

Processed 45 entities and 91 relations.

45 ent archive
SNAP AFL Coverage-Guided Fuzzing Coverage Tracing Hardware-Assisted Fuzzing Source Code Instrumentation Dynamic Binary Instrumentation Intel Processor Trace Coverage Bitmap Edge Coverage CPU Pipeline Speculative Execution Branch Prediction Bitmap Update Queue Last Branch Queue RISC-V BOOM RISC-V Control Flow Tracing Data Flow Analysis Binary Rewriting RetroWrite QEMU Micro-architectural State Basic Block Hardware Primitives FPGA Taint Analysis Control and Status Registers Memory Request Aggregation Opportunistic Bitmap Update Binutils PHMon Hardware Support to Improve Fuzzing Performance and Precision Ren Ding Yonghae Kim Fan Sang Wen Xu Gururaj Saileshwar Taesoo Kim Georgia Institute of Technology Trace Decision Logic Edge Encoding Out-of-Order Execution Synopsys Design Compiler SPEC CPU2006
03
LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation

Processed 35 entities and 52 relations.

35 ent archive
LLM4DV Test Stimuli Generation Constrained-Random Testing Design Verification Functional Coverage Coverage Plan Coverage Bin LLM4DV Framework Coverage-Feedback Prompting Template Missed-Bin Sampling Best-Iterative-Message Sampling Dialogue Restarting Design-Under-Test Primitive Data Prefetcher Core Ibex Instruction Decoder Ibex CPU RISC-V GPT-3.5-turbo-0613 Llama 2 7B Verilator cocotb Assertion-Based Verification Concolic Testing Large Language Model RTL Zixi Zhang Greg Chadwick Hugo McNally Yiren Zhao Robert Mullins University of Cambridge lowRISC Imperial College London Coverpoint Type-based Sampling Mixed Coverpoint Type-based and Pure Random Sampling
01
MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

Processed 42 entities and 49 relations.

42 ent archive
MicroTESK Test Program Generation Architecture Description Language Instruction Set Model Test Knowledge Test Templates Constraint Satisfaction Problem Functional Verification Model-Based Testing Reconfigurable Test Program Generator Genesys-Pro RAVEN Z3 Solver SMT-LIB nML Sim-nML Test Template Description Language Coverage Model Graph-Based Functional Test Generation SAT-Based Bounded Model Checking Cache Memory Modeling Configuration Files MIPS Instruction Set Architecture Microprocessor Architecture Model EXPRESSION ADL Ruby Scripting Language Alexander Kamkin Andrei Tatarnikov Prabhat Mishra Nikil Dutt Heon-Mo Koo Institute for System Programming of RAS IBM Research Lab Obsidian Software Inc. Microsoft Research MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors Reconfigurable Model-Based Test Program Generator for Microprocessors Graph-Based Functional Test Program Generation for Pipelined Processors Functional Test Generation using SAT-based Bounded Model Checking SMT-Based Test Program Generation for Cache-Memory Testing Memory Management Unit Pipeline Control Unit
03
#ndss2026 #hardwaresecurity #fuzzing #processorsecurity ...

Processed 30 entities and 41 relations.

30 ent archive
ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits Fuzzilicon: A Post-Silicon Microcode-Guided x86 CPU Fuzzer GoldenFuzz: Generative Golden Reference Hardware Fuzzing ReFuzz Fuzzilicon GoldenFuzz processor fuzzing contextual bandits test mutation post-silicon fuzzing microcode-level instrumentation coverage-guided fuzzing golden-reference model fuzzing microarchitectural vulnerability detection hardware security x86 CPU RISC-V microcode Chen Chen Zaiyan Xu Mohamadreza Rostami David Liu Dileep Kalathil Ahmad-Reza Sadeghi Jeyavijayan Rajendran Johannes Lenzen Lichao Wu Huimin Li Nikhilesh Singh NDSS 2026
04
[PDF] Methodologies for Accelerated Open-Source Hardware Verification ...

Processed 67 entities and 69 relations.

67 ent archive
Condominium BlackParrot FPGA emulation RTL simulation coverage-guided fuzzing high-fidelity coverage metric ISA cosimulation cycle-accurate performance profiling latency-aligned group-coverage CAM-based Group Coverage Engine (CCE) automated coverage instrumentation formal verification clock-gating mechanism architectural checkpointing random constrained testing ISA compliance testing coverage-guided hardware fuzzing FPGA-accelerated coverage collection test stimulus generation sliding-window EXP3 multi-armed bandit bug injection black-box fuzzing PC generation instruction cache branch prediction cache coherence performance counters system-call abstraction heterogeneous prototyping cluster Zynq-based architecture Verilator RISC-V ISA scale-down prototyping AXI interface DPI-C interface PL-Shell functional verification continuous integration Linux boot BaseJump STL synthesized hardware probes FPGA bitstream generation Farzam Gilani Michael Taylor Mark Oskin Daniel Petrisko Anoop Mysore Nataraja Bespoke Silicon Group University of Washington covergroup coverpoint RTL datapath benchmark suite SPEC benchmark CoreMark instructions-per-clock (IPC) pipeline stall attribution non-intrusive emulation progressive coverage BRAM-based coverage engine one-to-one coverage mapping PYNQ API Vivado GDB Bedrock coherence protocol virtual-to-physical address translation catch-up ALU
01
Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022

Processed 30 entities and 44 relations.

30 ent archive
Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V S Pawan Kumar Shrreya Singh Neel Gala Allen Baum InCore Semiconductors IIT Gandhinagar Esperanto Technologies Architectural Testing RISC-V ISA Coverage Specification Signature-Based Testing Design Verification Coverpoint Data Propagation Analysis Constraint Satisfaction Problem Min-Conflict Solver Backtracking Solver SMT Solver-Based Test Generation Mutation-Based Test Generation Negative Testing Directed Test Generation RISCV-ISAC RISCV-CTG CGF Format RTL UVM Test Format Specification RISC-V Architectural Test Suite Directed Test Generation
02
Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors

Processed 37 entities and 47 relations.

37 ent archive
Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors Heon-Mo Koo Prabhat Mishra Intel Corporation University of Florida Directed Test Generation Random Test Generation Biased-Random Test Generation FSM Coverage-Directed Test Generation Test Compaction Dynamic Test Compaction Static Test Compaction Finite State Machine (FSM) Model FSM State Coverage FSM Transition Coverage Pipeline Interaction Coverage Functional Coverage Unreachable State Identification Illegal State Transition Identification Redundant State and Transition Elimination Inevitable State Model Checking for Test Generation Architecture Description Language (ADL) Temporal Logic Property Counterexample-based Test Generation RTL Implementation Simulation-based Validation Functional Fault Set Covering Fault Simulation Genesys-Pro MIPS Processor Model (FSM) e500 Processor Model (FSM) Pipelined Processor Functional Validation ISA-level Test Program Generation Path Selection in FSM Regression Testing
03
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Processed 49 entities and 39 relations.

49 ent archive
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study Heon-Mo Koo Prabhat Mishra Jayanta Bhadra Magdy Abadir University of Florida Freescale Semiconductor Inc. micro-architectural test generation directed test generation simulation-based validation instruction set architecture (ISA) random test generation biased-random test generation pipeline interaction fault temporal logic properties decompositional model checking counterexample generation processor model decomposition Linear Temporal Logic (LTL) finite state machine (FSM) model state-space explosion pipeline graph coverage functional fault model data forwarding register renaming out-of-order execution dynamic scheduling dynamic speculation superscalar processor reservation station reorder buffer completion queue clock-based counterexample integration test compaction RTL simulation SAT-based bounded model checking micro-architectural fault temporal specification language pipelined processor model Cadence SMV model checker Power Architecture Technology e500 processor MIPS processor deeply pipelined architecture property decomposition graph-based functional test program generation FSM model partitioning instruction-level parallelism
04
[PDF] HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs ...

Processed 58 entities and 72 relations.

58 ent archive
HARTBREAKER determinism anchors control-flow anchors data-flow anchors synchronization anchors differential testing pre-silicon fuzzing litmus tests non-determinism control-flow non-determinism data-flow non-determinism RVWMO memory consistency model inter-processor interrupts program-level determinism Preserved Program Order rules multi-hart CPU instruction set simulator RTL simulation CLINT store buffer Sequential Consistency Coherence of Read-Read microarchitectural state space exploration instruction throughput Cascade RISCV-DV DifuzzRTL TestRIG ProcessorFuzz INSTILLER TheHuzz MorFuzz RISCVuzz Spike Verilator UVM Rocket BOOM Toooba NaxRiscv XiangShan Quentin Bordier Tobias Kovats Flavien Solt Kaveh Razavi ETH Zurich UC Berkeley RISC-V MCM solver landing zone load value axiom syntactic dependency speculative execution out-of-order execution mret instruction MIP register HARTBREAKER paper
05
ISA specification – Related Work – Interesting papers - Alastair Reid

Processed 89 entities and 106 relations.

89 ent archive
Instruction Set Architecture CPU Verification Binary Analysis Binary Lifting ISA Semantics ISA Specification Processor Description Language Instruction Encoding Instruction Decoding Microarchitecture Simulation Instruction Set Simulator Formal Verification of Processors Memory Consistency Model Peephole Superoptimization Disassembly Code Generation Abstract Interpretation Instruction-Level Abstraction Axiomatic Concurrency Model Microcode Verification Reverse Engineering of Instruction Encodings System-on-Chip Verification Capability Architecture RTL Verification Hypervisor Verification Instruction Set Processor (ISP) Description Binary Translation Test Oracle Spectre/Microarchitectural Side Channel Sail ISA Specification Language Arm Architecture Specification Language (ASL) L3 Specification Language LISA Machine Description Language SLED (Specification Language for Encoding and Decoding) nML QEMU TCG (Tiny Code Generator) Intermediate Representation BAP (Binary Analysis Platform) BinRec Binary Lifter McSema Binary Lifter Remill Binary Lifting Library Capstone Disassembler Zydis x86 Decoder/Disassembler Library Dagger Binary Lifter LLVM-MCtoLL Binary Lifter reopt Binary Lifter rev.ng Reverse Engineering Tool Isla ISA Semantics Tool x86isa ISA Model (ACL2) UCLID5 TSL (Transfer Specification Language) Pydgin Instruction Set Simulator Generator ZSim Architectural Simulator HOIST Static Analyzer Derivation System ISA-Formal New Jersey Machine-Code Toolkit RockSalt SFI Tool Vale Cryptographic Assembly Verifier Examiner ARM Emulator Consistency Checker ARM Architecture RISC-V Architecture x86/x86-64 Architecture POWER Architecture CHERI Capability Architecture ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS (armstrong:popl19:2019) Detailed Models of ISAs: From Pseudocode to Formal Semantics (armstrong:arw:2018) Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models (armstrong:cav:2021) A Complete Formal Semantics of x86-64 User-Level ISA (dasgupta:pldi) End-to-End Verification of ARM Processors with ISA-Formal (reid:cav:2016) Trustworthy Specifications of ARM v8-A and v8-M System Level Architecture (reid:fmcad:2016) Who Guards the Guards? Formal Validation of the ARM v8-M Architecture Specification (reid:oopsla:2017) Automatic Generation and Validation of Instruction Encoders and Decoders (xu:cav:2021) Automated Synthesis of Symbolic Instruction Encodings from I/O Samples (godefroid:pldi:2012) Synthesizing Formal Models of Hardware from RTL for Efficient Verification of Memory Model Implementations (hsiao:micro:2021) Instruction-Level Abstraction (ILA): A Uniform Specification for SoC Verification (huang:todaes:2019) Modelling the ARMv8 Architecture Operationally: Concurrency and ISA (flur:popl:2016) Simplifying ARM Concurrency: Multicopy-Atomic Axiomatic and Operational Models for ARMv8 (pulte:popl:2017) Solver Aided Reverse Engineering of Architectural Features (zorn:iscawddd:2017) Reverse-Engineering Instruction Encodings (hsieh:usenix:2001) Executable ISA Model Pseudocode-to-Formal-Semantics Translation Symbolic Execution for ISA Testing Retargetable Code Generation Meta-Tracing JIT Compilation for ISS Axiomatic Hardware-Software Contracts Machine Code Decompilation Abstract Transfer Function Derivation Separation Logic for Machine Code Instruction Fuzzing / Differential Testing
06
MA2TG: A Functional Test Program Generator for Microprocessor Verification

Processed 28 entities and 23 relations.

28 ent archive
MA2TG Automatic Test Program Generation Constraint Satisfaction-based Test Generation Random Test Program Generation Architecture Description Language Functional Verification Microprocessor Architecture Modeling Specification-driven Test Generation User Constraints File DLX Processor MA2TG: A Functional Test Program Generator for Microprocessor Verification Tun Li Danni Zhu Yang Guo Gongjie Liu Sikun Li National University of Defense Technology AVPGEN EXPRESSION BNF-based Test Program Generation Graph-based Functional Test Program Generation Pipelined Processor Verification Prabhat Mishra Nikil Dutt Eyal Bin Avi Ziv Aharon Aharon PowerPC Processor Verification
02
CRAVE: An Advanced Constrained Random Verification Environment for SystemC

Processed 43 entities and 47 relations.

43 ent archive
CRAVE SCV Constrained Random Verification Stimuli Generation Electronic System Level Design SystemC Transaction Level Modeling Universal Verification Methodology BDD-based Constraint Solving SAT-based Constraint Solving SMT-based Constraint Solving Portfolio Constraint Solving metaSMT Z3 MiniSAT CUDD Boolector PicoSAT SWORD AIGER Dynamic Constraint Management Inline Constraints Incremental Constraint Specification Over-constraint Analysis randv<T> rand_obj rand_vec<T> Generator System-on-Chip Five-Stage Pipeline CPU CISC CPU Program Input Generation Simulation-based Equivalence Checking RTL Bubble Sort Input Generation ALU Constraint Verification Finn Haedicke Hoang M. Le Daniel Große Rolf Drechsler University of Bremen DFKI GmbH CRAVE: An Advanced Constrained Random Verification Environment for SystemC
03
https://arxiv.org/pdf/2211.00828

Processed 49 entities and 57 relations.

49 ent archive
GENESYS Covariance Matrix Adaptation Evolution Strategy Program Synthesis Continuous Optimization Machine Programming Bin Mapping Domain Specific Language Restart Policy Neural Program Optimization DeepCoder PCCoder RobustFill PushGP NetSyn Multivariate Normal Distribution Autoencoder Genetic Programming Genetic Algorithm Single Group Mapping Multi-Group Mapping Dynamic Bin Mapping Token Probability LSTM Cumulative Step-Size Adaptation Covariance Matrix Error Function Input-Output Examples IPOP Restart Strategy BIPOP Restart Strategy Reinforcement Learning Formal Program Synthesis Stochastic Superoptimization Shantanu Mandal Todd A. Anderson Javier Turek Justin Gottschlich Abdullah Muzahid Nikolaus Hansen Texas A&M University Intel Labs Merly AI Synthesizing Programs with Continuous Optimization Shgo Syntax-Guided Synthesis FlashFill Neural Network Markov Chain Monte Carlo Beam Search Depth-First Search
04
https://www.usenix.org/system/files/sec24summer-prepub-285-solt.pdf

Processed 45 entities and 53 relations.

45 ent archive
Cascade DifuzzRTL TheHuzz RFUZZ Spike Yosys CPU fuzzing asymmetric ISA pre-simulation differential fuzzing program reduction control flow entanglement with data flow RISC-V program generation RISC-V instruction set architecture (ISA) RTL simulation instruction set simulator (ISS) basic block control register coverage multiplexer select coverage program non-termination as bug detection fuzzing prevalence test case completion formal verification cf-ambiguous instruction offset applier instruction privilege transitions Control and Status Registers (CSRs) Floating-Point Unit (FPU) memory management in program generation dependency chain ELF file Cascade: CPU Fuzzing via Intricate Program Generation Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich VexRiscv PicoRV32 Kronos CVA6 Rocket BOOM HypFuzz Cascade Python implementation differential fuzzing
05
\tool: Differential testing with LLMs using Natural Language Specifications and Code Artifacts

Processed 30 entities and 52 relations.

30 ent archive
DiffSpec Differential Testing Prompt Chaining Large Language Model Instruction Set Architecture eBPF WebAssembly eBPF ISA Specification WebAssembly Language Specification eBPF Verifier eBPF JIT Compiler RSH Instruction Linux ARM32 eBPF Implementation ebpf-for-windows Kernel Memory Leak Fuzzing LKL-fuzzer BRF BVF Kgent DITWO WADIFF Wasmaker TitanFuzz Fuzz4All Mokav AID Wasm Validator Natural Language Specification eBPF Bytecode Test
06
GenHuzz: An Efficient Generative Hardware Fuzzer

Processed 43 entities and 64 relations.

43 ent archive
GenHuzz Hardware-Guided Reinforcement Learning Proximal Policy Optimization whitebox fuzzing coverage-based fuzzing differential testing reinforcement learning RISC-V assembly generation RISC-V ISA RTL Device Under Test Golden Reference Model hardware coverage Physical Memory Protection finite state machine coverage test case generation language model-based fuzzer GPT-2 Spike Synopsys VCS DifuzzRTL TheHuzz ChatFuzz Cascade RocketChip Boom CVA6 fuzzing policy reward function instruction semantics transformer architecture Generative Pre-trained Transformer Byte-Pair Encoding false positive detection Load-Reserved Store-Conditional Lichao Wu Mohamadreza Rostami Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi Technical University of Darmstadt Texas A&M University GenHuzz: An Efficient Generative Hardware Fuzzer
01
Differential analysis of x86-64 instruction decoders

Processed 17 entities and 18 relations.

17 ent archive
MISHEGOS Differential Fuzzing x86-64 Instruction Decoding Difference Oracle Sliding Window Fuzzing Strategy Overapproximated Machine Instruction Model Variable-Length Instruction Architecture Decoding Discrepancy Differential Analysis of x86-64 Instruction Decoders William H. Woodruff Niki Carroll Sebastiaan Peters Trail of Bits George Mason University Eindhoven University of Technology x86-64 N-Version Disassembly
02
Bug hunting SoC designs to achieve full functional coverage closure

Processed 42 entities and 54 relations.

42 ent archive
System on Chip (SoC) Constrained Random Verification (CRV) Directed Verification Functional Coverage Random Stimulus Generation Design Under Test (DUT) AXI Protocol Cache Coherency Stashing RTL Simulation Backdoor Access Front Door Access Coverage-Driven Verification Cross Coverage Stimulus Base Class Transaction-Level Modeling Coverage Closure Regression Testing Automatic Test Pattern Generation L1/L2 Cache Constraint-Based Stimulus Generation Weight-Based Transaction Control Randomized Delay Injection Data Comparison via Backdoor Read Unaligned Address Testing Bus Arbitration Verification AXI Transaction ID Randomization Seed-Based Regression Grading SystemVerilog parameters.txt random_axi stimulus class Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming Constraint-Based Random Stimuli Generation for Hardware Verification Applying Constrained-Random Verification to Microprocessors Coverage Driven Constraint Random Verification Architecture Bug hunting SoC designs to achieve full functional coverage closure Vijeta Marwah Saurabh Mishra Freescale Semiconductor National Institute of Technology, Kurukshetra Uttar Pradesh Technical University Lucknow VEDANT Semiconductor
03
Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States

Processed 31 entities and 38 relations.

31 ent archive
DIG (Dynamic Instruction Generator) Dynamic Instruction Generation Functional Verification Random Instruction Generation RISC-V DV RISC-V Torture Instruction Set Simulator Processor Runtime Architectural State Test Instruction Stream Functional Coverage Intra-instruction Test Knowledge Inter-instruction Test Knowledge RISC-V VeeR EH2 Western Digital Zhejiang University HEXIN Technologies Co., Ltd Anlin Liu T.C. Lu Yuhao Xi Yangfan Liu Peng Liu MicroGP Genesys-Pro Constraint Satisfaction Problem (CSP) for Test Generation Coverage Directed Test Generation Bayesian Networks for Test Generation Evolutionary Assembly Program Generation SMT-solver State Generation Dark Instructions and Vulnerabilities Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States
04
G enesys : A Novel Evolutionary Program Synthesis Tool with Continuous Optimization

Processed 23 entities and 26 relations.

23 ent archive
Genesys Covariance Matrix Adaptation Evolution Strategy Program Synthesis Continuous Optimization Evolutionary Algorithm Grammatical Evolution Genetic Programming Restart Policy Mapping Scheme Shantanu Mandal Todd A. Anderson Javier S. Turek Justin Gottschlich Abdullah Muzahid Texas A&M University Intel Santa Clara University The three pillars of machine programming Program synthesis as latent continuous optimization PSB2 CMA-ES for one-class constraint synthesis Deduction-Guided Reinforcement Learning Conflict-Driven Learning
05
[PDF] RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction ...

Processed 54 entities and 63 relations.

54 ent archive
RISCSmith Cascade RISCV-DV Spike Verilator DIFUZZRTL DLFuzz TheHuzz MorFuzz INSTILLER RISC-V RTL Hardware Fuzzing Differential Testing On-the-fly Differential Analysis Rich Instruction Construction Instruction Modeling Constrained Random Instruction Generation Coverage-Guided Fuzzing Source Instrumentation Binary Search-Based Minimization Exception Carry-on Template Per-Instruction Logging UVM Formal Verification Pre-Silicon Verification NaN Boxing Strongly Typed Instruction Model Inter-Instruction Dependency Register and Memory Initialization RISC-V UnifiedDB GNU RISC-V Toolchain CPU PicoRV32 CVA6 VexRiscv Rocket XiangShan Kronos BOOM RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis Xudong Zhang Yuanliang Chen Zehong Yu Zhen Yan Fuchen Ma Dalong Shi Yu Jiang Tsinghua University Aviation Industry Corporation of China CHIPS Alliance OpenHW Group OpenXiangShan lowRISC
06
Two-Stage Hardware Fuzzer (TU Darmstadt)

Processed 24 entities and 26 relations.

24 ent archive
GoldenFuzz: Generative Golden Reference Hardware Fuzzing GoldenFuzz hardware fuzzing Golden Reference Model ISA-compliant test generation instruction block concatenation feedback-driven fuzzing coverage-guided fuzzing digital twin simulation two-stage fuzzing framework Device Under Test CVSS vulnerability scoring hardware vulnerability discovery RocketChip BOOM CVA6 BA51-H RISC-V Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi TU Darmstadt
03
DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs

Processed 15 entities and 29 relations.

15 ent archive
DIFUZZRTL DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs Differential fuzz testing Register-coverage guided fuzzing Cycle-sensitive register coverage guiding Asynchronous interrupt events handling Unified CPU input format with TileLink protocols TileLink Drop-in-replacement designs Finite state machine state transition identification OpenRISC Mor1kx Cappuccino RISC-V Rocket Core RISC-V BOOM Core OpenRISC RISC-V
03
Leakage Contracts for Processors with Transitions and Glitches

Processed 29 entities and 28 relations.

29 ent archive
Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches Johannes Haring Vedad Hadžić Roderick Bloem Graz University of Technology IAIK RISC-V Ibex RV32E RV32I Leakage contracts Glitch-aware leakage model Transition leakage Glitch leakage Value leakage Symbolic execution 2-safety hyperproperty verification Masking t-probing security Genoa MaskVerif scVerif Coco glitch-contracts leak step_cpu glitchy_decode regfile_glitches load_leakage
02
A RISC-V Test Sequences Generation Method Based on Instruction ...

Processed 26 entities and 16 relations.

26 ent archive
On a consistency testing model and strategy for revealing RISC processor's dark instructions and vulnerabilities Specification-based test program generation for MIPS64 memory management units Constrained random verification for RISC-V: Overview, evaluation and discussion Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging Towards specification and testing of RISC-V ISA compliance Open-source validation suite for RISC-V Data constraint generation technology for microprocessor instruction verification based on SMT solver Genesys-Pro: Innovations in test program generation for functional processor verification Enhancing the efficiency of Bayesian network based coverage directed test generation A reinforcement learning approach to directed test generation for shared memory verification Using a constraint satisfaction formulation and solution techniques for random test program generation Verifying instruction set simulators using coverage-guided fuzzing Constrained random verification Specification-based test program generation Randomized instruction stream generation Coverage-guided aging Data constraint generation Bayesian network-based coverage-directed test generation Reinforcement learning-based directed test generation Constraint satisfaction for random test program generation Coverage-guided fuzzing Genesys-Pro SMT solver Instruction set simulator RISC-V MIPS64
01
[PDF] Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing

Processed 31 entities and 32 relations.

31 ent archive
ChatFuzz TheHuzz DifuzzRTL HyPFuzz PSOFuzz RFUZZ MorFuzz DirectFuzz Hardware fuzzing Processor fuzzing Coverage-guided fuzzing Directed graybox fuzzing Differential fuzz testing Seed generation Mutation-based fuzzing Reinforcement learning (RL) PPO Large Language Models (LLMs) Hybrid hardware fuzzing Formal-assisted processor fuzzing Particle Swarm Optimization (PSO) Runtime instruction morphing LLM-based Input Generator ISA Disassembler GPT-2 Interdependent data/control-flow entangled instruction generation Machine code sequence generation Coverage feedback Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing Universal fuzzing via large language models Fuzzing hardware like software
01
EPEX: Processor Verification by Equivalent Program Execution

Processed 53 entities and 54 relations.

53 ent archive
EPEX Equivalent Program Execution Processor Verification Test Program Generation Equivalence Checking ISA-level Verification Architectural State Formal ISA Model RTL Instruction Set Architecture Instruction Set Simulator Constrained Random Test Generation Simulation-Based Verification Formal Verification Satisfiability Modulo Theories Program Synthesis Bounded Model Checking Symbolic Quick Error Detection Quick Error Detection Coverage-Guided Fuzzing Mutation Testing Control Path Variation Instruction Replacement Effect Constraint Chain Constraint Z3 SMT Solver CBMC riscv-formal OneSpin 360 DV RISC-V DV RISC-V Torture Test Generator VexRiscv SpinalHDL MicroTESK Genesys-Pro SMT-lib v2.0 Universal Verification Methodology RISC-V ISA Cross-Level Testing Compliance Test Suite Dhrystone Benchmark Instruction Sequence Equivalence EPEX: Processor Verification by Equivalent Program Execution Lucas Klemmer Daniel Große Johannes Kepler University Linz RISC-V Foundation Barrel Shifter Pipeline Stage Theorem Proving Bayesian Network Test Generation RISC-V Sail Model epex-formal-rv32-model
03
Corner Case Scenario Generation (CCSG) Tool: A Novel Approach to find corner case bugs in next generation SoCs

Processed 21 entities and 30 relations.

21 ent archive
Corner Case Scenario Generation Tool CCSG Corner Case Scenario Generation SoC Pre-Silicon Verification Mode Transition Verification Asynchronous Event Injection Multi-Power Domain Verification Multi-Mode Operation External Reset External Interrupt External Wakeup Clock Failure Precision Event Sweeping Post-Processing of Simulation Results Randomization of Asynchronous Events SoC Mode Control Module CCSG Verilog Implementation Low Power Mode Naveen Jakhar Department of Telecommunications, Government of India
04
MicroTESK: An Extendable Framework for Test Program Generation

Processed 47 entities and 67 relations.

47 ent archive
MicroTESK Test Program Generation Random Generation Combinatorial Generation Template-Based Generation Model-Based Generation Constraint-Based Random Generation RAVEN Genesys-Pro Instruction-Level Model Microarchitectural Model Architecture Description Language Sim-nML Test Template Test Situation Coverage Model Design Model Self-Checking Test Test Oracle SMT Solver Yices Z3 SMT-LIB Java Constraint Solver API Fault Model Operation State Machine Extended Finite State Machine Pipeline Model EXPRESSION ADL SMV Test Sequence Generator Test Data Generator Microprocessor Verification Instruction Set Architecture Memory Management ISPRAS IBM Research Obsidian Software Alexander Kamkin Tatiana Sergeeva Andrei Tatarnikov Artemiy Utekhin Test Template Processor Constraint Solver Engine MIPS Instruction Set Test Program Composition MicroTESK: An Extendable Framework for Test Program Generation
01
frestr/armshaker

Processed 23 entities and 22 relations.

23 ent archive
armshaker processor fuzzing hidden instructions undefined instruction exception exhaustive instruction space search SIGILL Armv8-A ISA A64 instruction set A32 instruction set T32 instruction set ptrace-based instruction execution multiprocessing fuzzing random register value initialization instruction mask-based targeted fuzzing libopcodes disassembler Capstone disassembler sandsifter Christopher Domas condition code matching undocumented instructions armshaker.py front-end fuzzer back-end shell_frontend.sh
02
Inside RISC-V: Navigating the RTL Design & Verification Landscape

Processed 39 entities and 55 relations.

39 ent archive
Suresh Chips and Semiconductor RISC-V Register Transfer Level (RTL) Instruction Set Architecture (ISA) Parameterization XLEN Pipeline Depth Branch Predictor Branch History Table (BHT) Branch Target Buffer (BTB) Cache Associativity AXI Bus Interface AHB Bus Interface TL-UL Bus Interface Physical Memory Protection (PMP) Smepmp Privilege Modes Cache Coherency Protocol RISC-V Weak Memory Ordering (RVWMO) Register Bypassing Speculative Execution Non-Blocking Cache Instruction Set Simulator (ISS) Spike QEMU Universal Verification Methodology (UVM) cocotb Design Under Test (DUT) Constrained Random Verification (CRV) Formal Verification (FV) SystemVerilog Assertions (SVA) UVM Sequence Layer Bus Functional Model (BFM) Scoreboard Verification IP (VIP) riscv_core RTL Module FPU (Floating Point Unit) Integer Multiply/Divide Unit Interrupt Controller
03
[PDF] Bringing CHERI Capabilities to Life in a Virtual Platform: CHERI ...

Processed 43 entities and 46 relations.

43 ent archive
CHERI RISC-V CHERI-RISC-V capability pointer memory safety buffer overflow use-after-free tagged memory capability bounds capability permissions capability tag bit monotonicity hybrid mode virtual prototype transaction-level modeling RTL simulation emulation QEMU SystemC design space exploration RISC-V VP++ CHERI-RISC-V VP++ instruction set simulator TLM tag extension virtual memory management TLB TestRIG Direct Instruction Injection RISC-V Formal Interface CHERI RISC-V Sail model RVVTS CheriBSD instruction overhead benchmark workload security analysis Manfred Schlägl Andreas Hinterdorfer Daniel Große Institute for Complex Systems A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture early software development RISC-V Vector Extension interpreter-based ISS
04
[PDF] Survey of Verification of RISC-V Processors

Processed 90 entities and 74 relations.

90 ent archive
RISC-V Functional Verification Formal Verification Coverage-Driven Verification Directed Tests Random Tests Constrained Random Stimulus Self-Checking Tests Instruction Set Simulator (ISS) Golden Reference Model Trace Log File Comparison Sync-Lock-Step Compare Async-Lock-Step Compare Instruction Stream Generator (ISG) Error Modelling Compliance Testing Signature-Based Test RTL Simulation Software-Based Self-Test (SBST) Burn-In Programs Benchmark Testing Hello World Test Verification Plan Functional Coverage Code Coverage Model Checking Theorem Proving Equivalence Checking Assertions Genetic Algorithm-Based Test Generation Binary Decision Diagrams (BDDs) Pseudo-Random Test Generation Cross-Level Testing RISC-V Verification Interface (RVVI) UVM (Universal Verification Methodology) OVM (Open Verification Methodology) SystemVerilog Testbench riscvOVPsim riscvOVPsimPlus ImperasDV riscv-formal RISC-V Torture Test Generator Shakti AAPG (Automated Assembly Program Generator) Google riscv-dv / COREV-DV riscvISACOV Jasper Formal Verification TestRIG Verilator SyDeKick PVS (Prototype Verification System) Chipyard μGP (Micro Genetic Program) RVVI-Trace RVVI-API RVVI-VVP (Virtual Verification Peripherals) Verification IP (VIP) Design Under Test (DUT) Instruction Set Architecture (ISA) Hardware Description Language (HDL) RTL (Register Transfer Level) FPGA Prototyping Emulation RISC-V International University of California, Berkeley Imperas OpenHW Group Cadence Siemens EDA Synopsys Google Chloe Tain Savita Patil Hussain Al-Asaad CORE-V-VERIF Testbench CV32E40P Rocket Core BOOM (Berkeley Out-of-Order Machine) Ibex (Zero-RISCV) CVA6 (Ariane) VexRiscv PicoRV32 SweRV (VeeR EL2) PULPino Hardware Design Verification (HW DV) Testbench Program Counter (PC) Monitoring Sail Specification Language CHERI Security Extension Chisel HDL CoreMark Benchmark
01
FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution

Processed 66 entities and 72 relations.

66 ent archive
FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution Aruna Jayasena Sai Suprabhanu Nallapaneni Prabhat Mishra University of Florida Hardware Fuzzing Coverage-Guided Fuzzing Selective Symbolic Execution Random Test Generation Constrained-Random Verification Property Checking Symbolic Execution Differential Fuzz Testing Semi-Formal Verification Formal Verification Coverage Plateau Branch Coverage Toggle Coverage State Space Explosion Hard-to-Activate Regions Control Flow Graph Finite State Machine Register-Transfer Level Fuzzing Corpus Test Vector Input Mutation Assembly Instruction Sequence Hardware Testbench Design Instrumentation Hardware-Program Context Mapping Source-Destination Pair Extraction SMT Solving Plateau Detection AXI-4 Interface SPI Interface Processor Validation Security Vulnerability Detection Doob Martingale Analysis Azuma-Hoeffding Inequality Cycle-Accurate Simulation VEX Intermediate Representation Register Coverage Metric Physical Memory Protection FuSS Framework Verilator angr Z3 SMT Solver EBMC DifuzzRTL TheHuzz HD-Fuzz ChatFuzz PSOFuzz ProcessorFuzz MABFuzz Cascade SurgeFuzz FormalFuzzer HyPFuzz SoCFuzzer PicoSoC UeRVSoC VeeRwolf CVA6 RISC-V Instruction Set Architecture System-on-Chip
02
A methodology for validation of microprocessors using equivalence checking - Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th Inte

Processed 40 entities and 54 relations.

40 ent archive
A Methodology for Validation of Microprocessors using Equivalence Checking Prabhat Mishra Nikil Dutt ACES Laboratory University of California Irvine Equivalence Checking Golden Reference Model EXPRESSION ADL Architecture Description Language Register Transfer Language Synthesizable HDL Generation Functional Abstraction Technique DLX Architecture Pipelined Processor Validation Logic Cones Compare Point Matching Theorem Proving Model Checking Unpipelining Verification Compositional Model Checking ADL-driven Validation Framework Pipeline Structure Specification Instruction Decoder Data Path Control Logic Synopsys Formality Design Space Exploration ISDL MIMOLA LISA ADL nML Abstract State Machine Hazard Detection Cadence Affirma Mentor FormalPro Verplex Conformal Embedded Systems Systems-on-Chip Hardware Description Language VHDL
04
GoldenFuzz: Generative Golden Reference Hardware Fuzzing - NDSS Symposium

Processed 25 entities and 33 relations.

25 ent archive
GoldenFuzz hardware fuzzing Golden Reference Model ISA-compliant test generation instruction block concatenation feedback-driven fuzzing coverage-guided fuzzing digital twin two-stage fuzzing framework Device Under Test inter- and intra-instruction quality RISC-V RocketChip BOOM CVA6 BA51-H CVSS v3 severity scoring architectural state exploration test case refinement Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi Technical University of Darmstadt