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+50 entities · +68 links — latest run (2026-09-07)
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2026-09-07
cs.rice.edu/~vardi
01
On Parallel Scalable Uniform SAT Witness Generation

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Constrained-Random Verification Uniform Stimulus Generation SAT Witness Sampling Almost-Uniform Sampling Random Hashing Universal Hashing XOR Hash Functions Conjunctive Normal Form Approximate Model Counting Functional Verification Design Under Verification Parallel Stimulus Generation Interval Propagation Markov Chain Monte Carlo Sampling Random Seeding of SAT Solver Weighted Binary Decision Diagram Independent Support Bounded Model Checking Leapfrogging Optimization UniGen2 UniGen UniWit ApproxMC BSAT Enumeration Belief Network Constraint Conversion CryptoMiniSAT RACE On Parallel Scalable Uniform SAT Witness Generation Supratik Chakraborty Daniel J. Fremont Kuldeep S. Meel Sanjit A. Seshia Moshe Y. Vardi Armando Solar-Lezama Mate Soos Mark Jerrum Leslie Valiant Vijay Vazirani Indian Institute of Technology Bombay University of California Berkeley Rice University Intel EstimateParameters Algorithm GenerateSamples Algorithm Parallel UniGen2 ISCAS89 Benchmark Circuits SMTLib Benchmarks r-wise Independent Hash Functions Dennard Scaling Belief Network Constraint Conversion
01
From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV

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RVVTS Automated Failure Categorization RISC-V Vector Extension Ara vector processor coverage-guided test generation single-instruction isolation positive testing negative testing RISC-V Vector Tests Generator RISCV-DV FORCE-RISCV Spike Verilator RTL verification functional coverage grammar-based test generation code minimization Machine State AraRunner Ara test harness CVA6 ELF binary SIMD constraint solving Universal Verification Methodology co-simulation riscvOVPsim Sail-RISC-V CHIPS Alliance Johannes Kepler University Linz DFKI Bremen Manfred Schlägl Jonas Reichhardt Daniel Grosse Valid Sequences test set Invalid+Valid Sequences test set failure mode category symbolic execution RISC-V Torture Test Generator RISC-V VP++ QEMU From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
02
Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking

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Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking Shoham Shitrit Sreepathi Pai University of Rochester GPU instruction set formal semantics mutation testing equivalence checking test suite generation model-based test generation bounded model checking stratified random sampling executable semantics PTX instruction set NVIDIA CBMC MUSIC SAIL K framework libFuzzer KLEE SeaHorn LLBMC MiniSAT CVC4 CVC3 mutation score counterexample generation floating-point arithmetic IEEE floating point semantics undefined behaviour non-determinism differential testing coverage-guided fuzzing dynamic symbolic execution litmus tests instruction set simulator SMT-LIB SAT/SMT solvers add.rm.ftz.sat.f32 C semantics test suite generation pipeline path coverage ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS A Complete Formal Semantics of x86-64 User-level Instruction Set Architecture ISA formal semantics x86 instruction set RISC-V ARMv8 instruction set subnormal floating point numbers differential symbolic execution LLVM
2026-09-03
arxiv:2601.07593v1
01
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation

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RTL verification stimuli generation test plan generation two-stage test plan generation framework testbench generation constrained random generation supervised fine-tuning Group Relative Policy Optimization GRPO with State Mutation tree-based branching mutation strategy mutation testing reinforcement learning for language models reward modeling random test generation functional equivalence checking retrieval-augmented generation iterative refinement multi-agent framework coverage-driven verification RTL design verification golden RTL pass rate mutation detection rate input stimuli sub-unit RTL verification reward sparsity advantage computation sequential circuit verification combinational circuit verification data contamination DeepSeek-R1 Claude-4.0-Sonnet DeepSeek-R1-distill-Qwen-7B LLaMA-3.1-405B Claude3.7-Sonnet ScaleRTL-32B DAPO GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation ScaleRTL: scaling LLMs with reasoning data and test-time compute for accurate RTL code generation VerilogEval: evaluating large language models for Verilog code generation BugGen: a self-correcting multi-agent LLM pipeline for realistic RTL bug synthesis VeriDebug Comprehensive Verilog Design Problems (CVDP) benchmark DeepSeekMath: pushing the limits of mathematical reasoning in open language models VeriContaminated: assessing LLM-driven Verilog coding for data contamination RTLLM: an open-source benchmark for design RTL generation with large language model DAPO: an open-source LLM reinforcement learning system at scale Decomposed prompting: a modular approach for solving complex tasks Dimple Vijay Kochar Nathaniel Pinckney Haoxing Ren Brucek Khailany Chenhui Deng MIT NVIDIA Research ScaleRTL dataset SFT training dataset GRPO-SMu training dataset testbench template
01
[PDF] GenHuzz: An Efficient Generative Hardware Fuzzer - USENIX

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GenHuzz Hardware-Guided Reinforcement Learning hardware fuzzing whitebox fuzzing differential testing Proximal Policy Optimization reinforcement learning coverage-based fuzzing RISC-V assembly instruction generation RISC-V ISA test case generation hardware coverage feedback intra-instruction semantics inter-instruction semantics reward function fuzzing policy mutation-based instruction generation Golden Reference Model RTL simulation Device Under Test word-level tokenization reset module for exploration-exploitation balance Physical Memory Protection Load-Reserved/Store-Conditional instructions cross-entropy loss minimization mismatch detection DifuzzRTL TheHuzz ChatFuzz Cascade Spike RISC-V ISA simulator RocketChip Boom CVA6 GPT-2 GPT-based language model fuzzer transformer architecture FSM coverage condition coverage line coverage Lichao Wu Mohamadreza Rostami Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi Technical University of Darmstadt Texas A&M University RISC-V 32/64-bit ISA training dataset instruction tokenization and encoding execution trace comparison coverage-based fuzzing
02
[PDF] RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential ...

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RISCVuzz Differential CPU Fuzzing Instruction Sequence Generation Bottom-Up Instruction Space Exploration Encoding-Based Instruction Filtering Majority Vote Differential Analysis Static Binary Compilation for Noise Removal Sandbox State Protection Lazy Page Mapping Alarm-Based Infinite Loop Prevention Post-Silicon Fuzzing RTL Fuzzing RISC-V ISA Architectural CPU Vulnerability Halt-and-Catch-Fire CPU Vulnerability GhostWrite RISC-V Vector Extension XTheadMemIdx Extension Instruction Space Coverage Non-Determinism in Instruction Effects Differential Fuzzing Physical Memory Write Primitive Virtual Memory Bypass Transient-Execution Attack MMIO Privilege Levels in RISC-V Paging and Virtual Memory Reproducer File Instruction Encoding Space CSR Instructions QEMU Cascade DifuzzRTL RISC-V Opcodes Repository Nix Build System rvv-bench RISCVuzz Client (C and RISC-V Assembly) RISCVuzz Server Runner Sandbox RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing Fabian Thomas Lorenz Hetterich Ruiyi Zhang Daniel Weber Lukas Gerlach Michael Schwarz CISPA Helmholtz Center for Information Security T-Head SiFive Scaleway T-Head XuanTie C906 CPU T-Head XuanTie C908 CPU T-Head XuanTie C910 CPU SiFive U54 CPU SiFive U74 CPU vse128.v Instruction Fuzzing Throughput Optimization Multi-Core Fuzzing Parallelization Sequence Length Scaling
01
Verify RISC-V Custom Instructions: From Spec to Sign-Off

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38 ent archive
RISC-V custom RISC-V instruction RTL ISA custom-instruction verification contract reference model constrained-random stimulus generation directed semantic tests functional coverage retirement-level lockstep co-simulation architectural state comparison at instruction retirement formal verification instruction-stream generation UVM CPU riscv-dv Spike Sail RISC-V Architectural Certification Tests ACT4 framework custom opcode space (custom-0 through custom-3) operand space partitioning register aliasing privilege mode verification decoder overlap checking software toolchain enablement CHIPS Alliance RISC-V International Alpinum Consulting XLEN CSR regression testing coverage closure instruction encoding exception and trap behaviour pipeline hazard verification data dependency stimulus vendor extension naming convention
02
Coverage Plan — Ibex Documentation 0.1.dev50+geede2fbbe documentation

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Instruction Category ALU Instruction Category Mul Instruction Category Div Instruction Category Branch Instruction Category Jump Instruction Category Load Instruction Category Store Instruction Category CSRAccess Instruction Category EBreakDbg Instruction Category EBreakExc Instruction Category ECall Instruction Category MRet Instruction Category DRet Instruction Category WFI Instruction Category Fence Instruction Category FenceI Instruction Category FetchError Instruction Category CompressedIllegal Instruction Category UncompressedIllegal Instruction Category CSRIllegal Instruction Category PrivIllegal Instruction Category OtherIllegal Instruction Category None Instruction Category Compressed Instruction Uncompressed Instruction Instruction Fetch Stage Instruction Decode Execute Stage Decompression RV32M Extension Zicsr Extension RISC-V ALU Illegal Instruction Exception Debug Mode Privilege Level M-mode ibex_pkg::OPCODE_OP ibex_pkg::OPCODE_OP_IMM dcsr.ebreakm dcsr.ebreaku
01
RISC-V Verification: A Guide to Co-Simulation

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Lockstep Co-Simulation Retirement-Level Lockstep Architectural State Instruction Retirement Asynchronous Events Step-and-Compare Methodology Constrained-Random Instruction Streams Directed ISA Tests Configurable State Mask Weak Memory Model Virtual Memory Operations CSR Side Effects RTL Reference Model Co-Simulation Harness Checkpoint and Seed Logging Randomised Interrupt Injection Mismatch Reporting RVVI RISC-V UVM ImperasDV ImperasFPM VCS Verdi Synopsys Imperas S. Davidmann A. Sutton L. Moore Understanding the RISC-V Verification Ecosystem RISC-V Processor Verification Requires the Full Toolbox SystemVerilog
2026-08-25
d-nb.info/1255631414
01
Advanced virtual prototyping for cyber-physical systems ...

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Vladimir Herdt Rolf Drechsler University of Bremen DFKI GmbH RISC-V Virtual Prototype (VP) SystemC TLM Instruction Set Architecture (ISA) RISC-V VP QEMU SPIKE RV8 gem5 Renode FORVIS GRIFT SAIL-RISCV ETISS Dynamic Binary Translation (DBT) Universal Verification Methodology (UVM) RISCV-DV Constrained-Random Test Generation Fuzzing-based Test Generation Compliance Testing RTL Verification Instruction Set Simulator (ISS) Instruction Stream Generator (ISG) Concolic Testing Symbolic Execution Coverage-Guided Fuzzing (CGF) Dynamic Information Flow Tracking (DIFT) RISC-V Torture Test Generator Formal Verification Stateful Symbolic Simulation Partial Order Reduction (POR) State Subsumption Reduction (SSR) Cross-Level Co-Simulation Intermediate Verification Language (IVL) KLEE SAGE S2E Angr libFuzzer AFL RVX Cyber-Physical Systems (CPS) Internet-of-Things (IoT) Mutation Testing Signature-Based Test Infrastructure High-Level Synthesis (HLS) Design Space Exploration GDB Remote Serial Protocol (RSP) Eclipse IDE Timing Model Just-in-Time Compilation (JIT) Control and Status Registers (CSRs) RISC-V Privileged Architecture Embedded Software Verification SiFive HiFive1 Board Linux Operating System FreeRTOS Zephyr RTOS RIOT OS Advanced Virtual Prototyping for Cyber-Physical Systems Using RISC-V
2026-08-23
llm.ics.jku.at/files
01
FP-RVVTS: Sail-guided Verification of

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FP-RVVTS Sail RISC-V RISC-V Floating-Point (FP) Instruction Verification Grammar-Based FP Instruction Sequence Generation Differential Execution Dependency-Based Test-Case Minimization Automated Failure Characterization Positive and Negative Test Generation Failure Isolation Functional Coverage Measurement NaN-Boxing RTL Design Verification Spike RISC-V VP++ QEMU SoftFloat FloppyFloat riscvOVPSim PULP ARA RISCV-DV Cascade Instruction Set Simulator (ISS) FP Exception Flag Generation Rounding Mode IEEE 754 Floating-Point Standard Cross-Level Testing Mutation-Based Compliance Testing UVM-Based Verification Environment Machine State Comparison FP Grammar Production Rules SailRunner ExecutionRunner Katharina Ruep Manfred Schlägl Daniel Große Johannes Kepler University Linz RISC-V International Dependency Annotations Test-Set Generation Sub-Flow Test-Set Execution Sub-Flow
02
GoldenFuzz: Generative Golden Reference Hardware Fuzzing - University of Bristol

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GoldenFuzz hardware fuzzing Golden Reference Model Device Under Test ISA compliance instruction block construction coverage-guided feedback test case refinement two-stage fuzzing framework digital twin RocketChip BOOM CVA6 BA51-H RISC-V GoldenFuzz: A Novel Two-Stage Hardware Fuzzing Framework Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi Internet Society
01
HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing | alphaXiv

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HiFuzz DifuzzRTL Cascade Hardware Fuzzing Constrained-Random Verification Mutation-Based Fuzzing Constructive Fuzzing Hierarchical Reinforcement Learning Reinforcement Learning Proximal Policy Optimization Semantic-Aware Basic Block Encoding Adaptive Coverage Reward Mechanism Upper Confidence Bound Multi-Armed Bandit Bidirectional LSTM Sparse Reward Problem Intrinsic Reward Coverage Masking Effect Design Under Test Golden Reference Model Program Agent Basic Block Agent Test Program Generation Instruction Set Architecture RISC-V Structured Tokenizer Dependency Chain Instruction Prevalence Hardware Coverage Formal Verification Out-of-Order Execution Rocket Core BOOM Core CVA6 Cascade: CPU Fuzzing via Intricate Program Generation DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs Proximal Policy Optimization Algorithms Between MDPs and Semi-MDPs: A Framework for Temporal Abstraction in Reinforcement Learning Finite-Time Analysis of the Multiarmed Bandit Problem F. Solt K. Ceesay-Seitz K. Razavi J. Schulman F. Wolski P. Dhariwal A. Radford O. Klimov R. S. Sutton D. Precup S. Singh P. Auer N. Cesa-Bianchi P. Fischer USENIX Security Symposium
02
[PDF] RISC Whisk: Unleashing the Power of Software Fuzzing on Hardware

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RISC Whisk Nandita Singh Matthew Hicks Angelos Stavrou Wenjie Xiong hardware fuzzing software fuzzing sparse memory matrix custom mutator input seed random instruction generator constraint block direct programming interface executable binary line coverage coverage-based verification functional verification formal verification emulation-based verification assertion-based verification FPGA-based verification RTL mutation tree instruction set architecture memory modeling wishbone interface black-box fuzzing white-box fuzzing feedback-based fuzzing Program Under Test AFL++ Verilator Picorv Sodor1 Sodor3 Sodor5 Mor1kx RISC-V OpenRISC 1000 architecture hardware-to-software translation Virginia Polytechnic Institute and State University RISC-V Foundation testbench design verification
02
An SPU Reference Model for Simulation, Random Test Generation and Verification

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Synergistic Processing Unit (SPU) Cell Processor Instruction Set Architecture (ISA) SPU Reference Model Random Test Case Generation Genesys Pro (GPro) Instruction Simulator Pipeline Simulator Verification Environment RTL Simulation Floating-Point Model IEEE 754 Floating-Point Standard Function Coverage DMA Transaction Self-Modifying Code ECC Error Handling Check-pointing Streaming I/O APUOP Common Definition File Mambo Full System Simulator COFF Format Assembler In-Order Processor Yukio Watanabe Balazs Sallay Brad Michael Daniel Brokenshire Hazim Shafi Daisuke Hiraoka Toshiba Corporation IBM Sony Computer Entertainment Inc. An SPU Reference Model for Simulation, Random Test Generation and Verification INTERPRETER_exec() APU_t struct Channel Access Transaction
03
End-to-End Verification of ARM Processors with ISA-Formal

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ISA-Formal ARM Limited Bounded Model Checking Formal Verification Simulation-Based Verification Instruction Set Architecture (ISA) Pipeline Forwarding Out-of-Order Execution Register Renaming Reorder Buffer Instruction Fusion Dual Issue Pipeline Abstraction Function Pipeline Follower End-to-End Verification Burch-Dill Flushing Refinement Completion Refinement Architecture Explorer Architecture Specification Language (ASL) ARM Architecture Reference Manual RTL (Register Transfer Level) SystemVerilog Subset Behaviour Checking Abstract Functions (Oracle-based Verification) Interface Properties Hand-Written Properties Instruction Sequence (Stimulus) Superscalar Processor Microcontroller (3-stage pipeline) Floating Point Unit (FPU) Monomorphization (Compiler Technique) Constant Propagation Alastair Reid End-to-End Verification of ARM Processors with ISA-Formal ARMv8-A Architecture ARMv8-M Architecture Unconstrained Opcode (Free Stimulus) Assumption-Based Bug Workaround Instruction Class Enumeration Micro-op (micro-operation)
01
LLM-based Processor Verification: A Case Study for ...

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LLM-based Processor Verification: A Case Study for Neuromorphic Processor simulation-based verification random test generation constrained random generation coverage-directed test generation coverage-directed test selection LLM-based test generation RAVEN RISCV-DV GPT-3.5 GPT-4 large language model domain specific architecture neuromorphic processor neuromorphic instruction set RISC-V Xuantie-C910 RTL simulation code coverage block coverage expression coverage toggle coverage ISA coverage prompt engineering hardware-aware test generation assembly test generation C program test generation novelty-driven verification Codex DAVE Chip-Chat ChipGPT design under test iterative test refinement functional verification branch prediction TrueNorth ISA extension method National University of Defense Technology University of Electronic Science and Technology of China Defense Innovation Institute Chao Xiao Lei Wang LLM-based verification workflow
01
Specification-Driven Testbench Development for

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stimulus generator testbench test sequence generation cycle-accurate formal specification control flow graph Hoare triple generalized FSM model FSM traversal multistimulus execution channel microoperation stage driver stage monitor mediator response checker coverage tracker parallel-pipeline design semi-formal verification functional coverage interlock coverage multistimulus coverage precondition postcondition RTL model CTESK SeC Institute for System Programming of the Russian Academy of Sciences Mikhail Chupilko Alexander Kamkin MIPS64-compatible microprocessor L2 cache model checking simulation-based verification
02
Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging

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Prelude Priming-Guided State Reconstruction Snapshot-Based Debugging Visibility Warm-Up Differential Testing Cycle-Accurate Replay Memory Footprint Analysis Scan-Chain-Based State Capture State Readback RTL Simulation FPGA-Based Prototyping Full-State Capture Micro-Architectural State Reconstruction Signal Tracing DESSERT ENCORE StateMover STATE-ACCESS VCS Verilator ILA SignalTap ChipScope Spike Xilinx Vivado BOOM Rocket RISC-V Out-of-Order Execution Architectural Registers Micro-Architectural State Pipeline Reorder Buffer (ROB) Branch Predictor Load-Store Queue (LSQ) Cache Hierarchy ISA Simulator RTL Signal Visibility Physical Register File DPI-C Interface PCIe Interface Data Extract Unit (DEU) Architectural Register Management Unit (AMU) Memory Rebuild Unit (MRU) AMD Virtex UltraScale+ VU19P FPGA CoreMark Embench Memory Footprint Instruction Set Architecture (ISA) Jialin Sun Yuchen Hu Dean You Zhe Jiang Xinwei Fang Southeast University University of York National Center of Technology Innovation for EDA Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging RISC-V DV ProcessorFuzz HyPFuzz Processor Fuzzing Instruction Fetch Unit (IFU) Program Counter (PC) General Purpose Registers (GPRs) Floating Point Registers (FPRs) Control and Status Registers (CSRs) UVLLM ISAAC MEIC RISCVuzz DiffTest-H Superscalar Processor Waveform Tracing Reproduction Rate
04
Specification-Based Test Program Generation for MIPS64 Memory Management Units

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Specification-Based Test Program Generation for MIPS64 Memory Management Units A.S. Kamkin A.M. Kotsynyak Institute for System Programming of the Russian Academy of Sciences MicroTESK test program generation memory management unit MIPS64 MMUSL Genesys-Pro DeepTrans address translation translation lookaside buffer cache memory symbolic execution constraint solving formal specification test template instruction set architecture nML directed acyclic graph execution path combinatorial test generation page table Ruby Z3 SMT solver CVC4 SMT solver Fortress library MA2TG random test generation domain-specific language instruction set simulator memory segment microprocessor verification test data generation IBM D. Vorobyev A. Tatarnikov buffer-event factorization preparator MicroTESK
01
Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs

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Constrained Random Verification Cross-Level Verification Mutation Testing Mutation Coverage Functional Coverage RTL Code Coverage Instruction Sequence Length Mutation Location Mutation Count Virtual Prototype Register-Transfer Level RISC-V Instruction Set Architecture Fuzzing Symbolic Execution Formal Verification Input Stimuli Generation Coverage-Guided Feedback SMT Solver Transaction Level Modeling Device Under Verification CRV Strategy Execution Trace Comparison Value Coverage Immediate Value Coverage Register File Access Coverage Saturation Feedback-Based Verification riscv-dv MicroRV32 Yosys RISC-V VP FORCE-RISCV RISC-V Torture Test RTL Mutation Engine Commercial RTL Simulator Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs Sallar Ahmadi-Pour Luca Müller Rolf Drechsler University of Bremen DFKI GmbH CHIPS Alliance ALU Control Unit Fetch Unit Instruction Decoder Multiply-Divide Unit System-on-Chip Binary-Compatible Executable Mutation Generation Scripts RTL Mutation Engine
01
An introduction to RISC-V processor verification techniques

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RISC-V Design Verification Post-simulation Trace File Compare Self-checking Tests Signature Comparison Step-and-Compare Step-and-Compare with Asynchronous Events Constrained Random Verification Functional Coverage Assertions Verification Planning Instruction Stream Generator Instruction Set Simulator Processor Reference Model RVVI RVVI-TRACE RVVI-API UVM RTL Simulation Co-simulation Verification IP Compliance Tests Asynchronous Events Metric-driven Verification Hybrid Verification Methodology riscvOVPsimPlus ImperasDV riscv-dv Valtrix STING spike riscvISACOV Imperas RVFCgen GCC LLVM Imperas Software RISC-V International OpenHW Group CHIPS Alliance EM Micro SiLabs Lee Moore Aimee Sutton core-v-verif RVVI GitHub Repository CV32E40X RISC-V ISA Extensions SystemVerilog DPI
01
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer

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RISC-V ISA (Instruction Set Architecture) UVM (Universal Verification Methodology) Golden Predictor Model Configuration Layer FlexMem Emulation RTL (Register Transfer Level) ISA Simulator CodAL Instruction-Accurate (IA) Model Cycle-Accurate (CA) Model Design Under Test (DUT) Scoreboard uvm_config_db Ifdef Constructs Functional Coverage Transactors Codasip Ltd. Mentor, A Siemens Business RISC-V Foundation University of California, Berkeley Marcela Zachariášová Luboš Moravec John Stickley Shakeel Jeeawoody Codasip Studio Veloce Emulator Questa RTL Simulator Codix Berkelium Processor SystemVerilog Random Test Generation UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
02
Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments

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Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments Waqas Ahmed Siegfried Brandstätter Mario Huemer Royal Institute of Technology (KTH) DMCE GmbH & Co KG Klagenfurt University Open Verification Methodology (OVM) Instruction Set Simulator (ISS) Golden Model Coverage-Driven Constraint Random Verification Functional Verification Formal Verification Register Transfer Level (RTL) Transaction-Level Modeling (TLM) Or1ksim OpenRISC1200 (OR1200) Directed Test Generation Constrained Random Instruction Generation Scoreboard Coverage Model OR1200 Wrapper OR1200 TB Pipeline Synchronization OR1200 Instruction Set ELF Image SystemC FIFO SystemVerilog ModelSim Mentor Graphics Cadence Design System Embecosm Harvard Memory Architecture Multiply-Accumulate (MAC) Unit Arithmetic Logic Unit (ALU) Load/Store Unit (LSU) General Purpose Registers (GPRs) OpenRISC32 C/C++ Compiler Reusable Verification Environment Interface Verification Component (IVC) System Verification Component (SVC) Virtual Sequencer OR1200 Wrapper OR1200 TB
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Automatic test program generation using extended conditional constraint satisfaction - Intranational Business Machines Corporation

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Constraint Satisfaction Problem Conditional Constraint Satisfaction Problem Extended Conditional Constraint Satisfaction Problem Automatic Test Program Generation Micro-architectural Model Design Under Test Operator Semantics Table Parse Tree Directed Acyclic Graph Shadow Variable Preserved Semantics Activation Requirement Random Test Program Generation Microprocessor Verification Piparazzi ECondCSP Builder CondCSP Solver Test Generator Algorithms for Constraint Satisfaction Problems: A Survey Using a Constraint Satisfaction Formulation and Solution Techniques for Random Test Program Generation Piparazzi: A Test Program Generator for Micro-architecture Flow Verification Kumar Bin Adir Compatibility Constraint Activity Constraint Micro-architectural Event Atomic Constraint Composition Method Compose Pseudocode
02
Artifact of Search+LLM-based Testing for ARM Simulators - Zenodo

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SearchSYS gem5 AFL++ Fuzzing Differential Testing LLM-based Test Generation ARM ISA Seed Corpus cm-gem5c.so cm-gem5c-bin.so cm-gem5c-types.so TinyLlama CodeBooga Magicoder Phi Llama GPT-3.5 Search+LLM-based Testing for ARM Simulators Karine Even-Mendoza Hector D. Menendez W.B. Langdon Aidan Dakhama Justyna Petke Bobby R. Bruce ARM Custom Mutator Binary Instrumentation hello-custom-binary-Ex.py 1-run-diff-test.sh 2-test-input.sh Experiment-ARM-24h.sh C Program Generation
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RiescueD User Guide — Riescue 1.14.0 documentation

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reset_pc memory map DRAM region IO region HTIF RV64 RISC-V I extension RISC-V M extension RISC-V A extension RISC-V F extension RISC-V D extension RISC-V C extension RISC-V H extension RISC-V V extension RISC-V U mode RISC-V S mode test generation secure access probability secure page table probability A/D bit randomization PBMT NCIO randomization feature randomization CPU stimulus configuration JSON
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An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors

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70 ent archive
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors Kathryn E. Gray Gabriel Kerneis Dominic Mulligan Christopher Pulte Susmit Sarkar Peter Sewell University of Cambridge University of St Andrews IBM POWER architecture ARM architecture weakly consistent multiprocessor architectural envelope model test oracle concurrency model ISA model gem5 QEMU Sail Lem ppcmem litmus test instruction description language (IDL) out-of-order execution speculative execution MP+sync+ctrl litmus test MP+sync+rs litmus test PPOCA litmus test LB+datas+WW litmus test MP+sync+addr-cr litmus test storage subsystem model register dependency mixed-size memory access non-multicopy-atomic architecture in-flight instruction tree pre-silicon testing post-silicon testing C/C++11 concurrency TSO memory model sequentially consistent multiprocessor x86 architecture POWER ISA fixed-point non-vector user-mode instruction set Sail type system vendor pseudocode XML extraction tool Framemaker document ELF executable format OCaml executable code Coq proof assistant HOL4 Isabelle/HOL Sail interpreter instruction decode function memory barrier instruction stdu instruction stw instruction lwz instruction coherence relation register footprint analysis condition register (CR) general-purpose registers (GPR) program order undefined value semantics dynamic taint tracking exhaustive behaviour exploration Anthony Fox system_state type micro_op_state type enumerate_transitions_of_system function web interface for model exploration
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Generating Distinguishing Tests using the MINION

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MINION Distinguishing Test Case Constraint Satisfaction Problem Static Single Assignment Form Loop Unrolling Mutation Testing Program Mutation Fault Localization Constraint-Based Test Data Generation Program-to-Constraint Compilation computeDistinguishingTest Algorithm Franz Wotawa Mihai Nica Bernhard K. Aichernig Technische Universität Graz CBMC Z3 SMT-solver Phi Function Variable Ordering Finite Domain
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Open source and CI-driven RTL testing and verification for ...

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riscv-dv Random Instruction Generation RTL Simulation Spike Instruction Set Simulator UVM Verilator cocotb pyuvm OpenOCD GDB JTAG Functional Coverage Continuous Integration Verible RISC-V RTL VeeR Execution Trace Log Parser NOP Injection Post-Processing Script cocotb Testbench for VeeR pyuvm UVM Agent for VeeR-EL2 Programmable Interrupt Controller Lazy Parsing Stimulus Generation CHIPS Alliance Antmicro Google VeeR EL2 Custom GitHub Actions Runners
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Search+LLM-based Testing for ARM Simulators - SOLAR UCL

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SearchSYS gem5 AFL++ Fuzzing Differential Testing Large Language Model CodeLlama TinyLlama Phi2 Llama2 Magicoder CodeBooga GPT-3.5-turbo Ollama ARM Instruction Set Architecture ARMv8 X86 ISA RISC-V Zero-shot Prompting Prompt Engineering Coverage-Guided Fuzzing Mutation-Based Testing Search-Based Software Testing Seed Generation Test Suite Generation Regression Testing Binary Mutation C Program Generation ARM King's College London University College London University of California, Davis Karine Even-Mendoza Héctor D. Menéndez W.B. Langdon Aidan Dakhama Justyna Petke Bobby R. Bruce ChatFuzz Fuzz4All ROCODE OSS-Fuzz Oracle Problem Continuous Integration Testing Compiler Optimization Tokens Phind-CodeLlama-34B-v2 WizardCoder-Python-34B-V1.0 Google Meta Parametrized Input Generation
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[PDF] Efficient Cross-Level Processor Verification using Coverage-guided ...

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Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing Niklas Bruns Vladimir Herdt Daniel Große Rolf Drechsler University of Bremen DFKI GmbH Johannes Kepler University Linz Coverage-Guided Fuzzing Cross-Level Processor Verification RTL Processor Verification Co-Simulation Instruction Set Architecture Mutation-Based Test Generation Processor-Level Input Stimuli Generation AFL LLVM libFuzzer RISC-V VexRiscv RISC-V VP Instruction Set Simulator Translation Buffer Execution Controller Fast Exploration Mutation Enhanced Havoc Mutation Test Vector Clustering Post-Processing Virtual Coverage Edge Coverage Register Value Comparison Verilator SystemC TLM SpinalHDL Constraint Satisfaction Problem Model-Based Test Generation Symbolic Execution Bitflip Mutation Arithmetic Mutation Havoc Mutation CSR Testing RV32IM Infinite Loop Prevention RFUZZ SpinalFuzz RISCV-DV RISC-V Torture Test Generator Genesys-Pro Bayesian Network Test Generation FPGA Acceleration for Fuzzing Mann-Whitney U Test Endless Instruction Stream Generation
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https://riscv-europe.org/summit/2023/media/proceedings/posters/2023-06-07-Fatima-SALEEM-abstract.pdf

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53 ent archive
RISC-V Vector Extension RVV Specification v1.0 RVV Specification v0.9 Architecture-level Verification Vector Instruction Test Suite VLEN LMUL SEW Signature-based Checking Self-Checking Tests Instruction Set Architecture Compliance Testing Random Instruction Generation Automatic Test Generation Imperas Vector Test Suite riscvOVPsim RIOS Labs Vector Test Generator RISCOF RISC-V Torture RISC-V DV FORCE-RISCV Yang's Vector Test Generator Tenstorrent Vector Test Suite Spike ISA Simulator Sail ISA Simulator Handcar ISS Whisper ISS RISCV-ISAC Renode UVM-based Random Instruction Generation Instruction Sequence Generation Coverage-driven Verification GoLang Test Generator Scala-based Test Generator 10xEngineers Imperas RIOS Labs Andes Google Antmicro PLCT Lab Tenstorrent chipsalliance openhwgroup Fatima Saleem Umer Imran Quswar Abid Kamran Malik Yang Liu Open-Source RISC-V Vector Test Suites: A Comparative Analysis RTL Verification RISC-V ISA Vector Register GNU Make
02
Cross-Level Verification of Hardware Peripherals

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25 ent archive
Coverage-Guided Fuzzing Co-Simulation Virtual Prototype Transaction Level Modeling RTL RISC-V Platform Level Interrupt Controller RISC-V VP LLVM libFuzzer Verilator SpinalHDL Tracalyzer TLM-RTL Transactor Design Under Verification Cross-Level Verification Coverage Metric FreeRTOS Sallar Ahmadi-Pour Muhammad Hassan Rolf Drechsler University of Bremen DFKI GmbH Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation System-on-Chip Coverage-Guided Fuzzing Co-Simulation
03
Design and Application of a Co-Simulation Framework for Chisel

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58 ent archive
Design and Application of a Co-Simulation Framework for Chisel Ryan Lund Borivoje Nikolic Krste Asanovic Anson Tsai John Wright Paul Rigge Vighnesh Iyer University of California, Berkeley Co-Simulation Framework for Chisel (CFC) Chisel ChiselTest Chipyard Gemmini Spike FireSim Dromajo Vitis HLS ISim HDL Verifier Rocket Chip BOOM Protocol Buffers (protobufs) Co-Simulation Instruction-Accurate Simulation RTL Simulation Mixed-Abstraction Verification Mixed-Signal Verification Mixed-Medium Verification Cycle-Accurate Simulation Phase-Accurate Simulation Pre-Silicon Verification Tandem Simulation Out-of-Context Elaboration Diplomacy Parameter Negotiation Stimulus Generation Interprocess Communication (IPC) via Named Pipes Binary Caching Design Space Exploration RoCC Interface RISC-V ISA FPGA Emulation Protobuf-to-Bundle Conversion Bundle-to-Protobuf Conversion ProtoToBundle BundleToProto BundleToJson PipeDriver PipeMonitor CosimTester Trait getVerifParameters VerifRoCCStandaloneWrapper CosimTestUtils.scala VerifRoCCStandalone.scala Mathworks Xilinx Esperanto Technologies Google
04
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side

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57 ent archive
RISC-V Compliance Testing Negative Testing Positive Testing Coverage-Guided Fuzzing LLVM libFuzzer Test Program Generation Instruction Set Architecture (ISA) RTL Simulation UVM Constrained-Random Test Generation RISCV-DV riscvOVPsim Spike RISC-V VP GRIFT sail-riscv riscv-formal OneSpin 360 DV RISC-V Verification App RISC-V Torture Test Generator MicroTESK Fuzzing-Based Test-Suite Generation Custom Coverage Metric Custom Fuzzing Mutator Static Analysis Filter Bytestream Test-Case Template Compliance Signature Hash-Based Coverage Structural and Value Coverage Rules Instruction Decoder Verification Illegal Instruction Handling Control and Status Registers (CSRs) Privileged ISA ELF Format Constraint Solving Bayesian Network-Based Test Generation Machine Learning-Based Test Generation Model Checking Abstract Local Execution Instruction Set Simulator (ISS) Virtual Prototype Clang Compiler Instrumentation Vladimir Herdt Daniel Große Rolf Drechsler DFKI GmbH University of Bremen Imperas UC Berkeley Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side RV32I RV32IMC RV32GC Trap Handler Verilator Genesys-Pro
05
Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor

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DiffTest DiffTest-H Differential Testing Co-simulation Semantic-Aware Communication RTL Simulation Hardware-Accelerated RTL Simulation Batch Packaging Squash Compression Replay Debugging Structural Semantics Sequential Semantics Behavioral Semantics Verification Event Software-Hardware Communication Overhead Agile Verification NEMU ENCORE Fromajo Palladium FPGA RISC-V RTL DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Co-Simulation Xiangshan MICRO 2022 Paper Yu Zihao Shi Kan Bao Yungang Institute of Computing Technology, Chinese Academy of Sciences Beijing Open Source Chip Research Institute Xiangshan Team Xiangshan Processor Design Under Test Reference Model Architectural State PCIe
06
Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks

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Fault Injection Simulation Hash-based Differential Fault Effect Equivalence Check (CDIF+FEEC) Checkpoint Restore Boot (CRB) Statistical Fault Injection (SFI) Fault Equivalence Pruning (FEP) Dynamic Fault Collapsing (DFC) Mixed-level Simulation (MLS) Checkpoint Masking (CMSK) Checkpoint Differential (CDIF) Fault Effect Equivalence Check (FEEC) Register Transfer Level (RTL) Instruction Set Simulator (ISS) Instruction Set Architecture (ISA) Single Event Upset (SET) Silent Data Corruption (SDC) Detectable Unrecoverable Error (DUE) Database of Diffs (DoD) Database of Diff Hashes (DoH) Fault Space flip-flop-level fault injection Fault Outcome Prediction (FOP) Coordinate List Format (COO) ISO 26262 Verilator vRTLmod verilated RTL (vRTL) ARCHIE ETISS-ML EmbenchTM cv32e40p RISC-V System on Chip (SoC) micro-architectural state Johannes Geier Leonidas Kontopoulos Daniel Mueller-Gritschneder Ulf Schlichtmann L. Berrojo Technical University of Munich TU Wien OpenHW Group Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks server-client simulation framework golden reference simulation Hamming Weight collision-free hash function
01
The Sail instruction-set semantics specification language

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26 ent archive
BNF Grammar Type System Type Variable Type Quantifier Kind Annotation Pattern Matching Expression Language Register Type Bitfield Type Effect System Function Definition Mapping Definition Struct Type Enum Type Union Type Overload Definition Instantiation Scattered Definition Termination Measure Let Binding Attribute Annotation Vector Type Bitvector Literal Value Specification Extern Binding Sail ISA Specification Language
02
Minimal Stimuli Generation in Simulation-based Verification

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43 ent archive
Simulation-based Verification Constraint-based Stimuli Generation Minimal Stimuli Generation Coverage-driven Verification Functional Coverage Boolean Satisfiability (SAT) SAT-based Stimuli Generation Tseitin Transformation Iterative Stimuli Generation Naive Stimuli Generation Random Constraint-based Simulation Parallel Simulation for Multiple Scenarios Boolector Algorithm 1: Minimal Stimuli Generation Design Under Verification (DUV) Coverage Metrics Scenario-based Verification RISC Processor Program Counter (PC) Arithmetic Logic Unit (ALU) Control Unit (CU) Memory Management Unit (MMU) ALU Reduced External Data Memory (RAM) Stack Harvard Architecture SMT-based Stimuli Generation Bounded Model Checking Automatic Constraint Generation Random Stimulus Generation Coverage-driven Stimuli Generation (Yang et al., 2012) HW/SW Co-Verification using Bounded Model Checking (Große et al., 2006) SMT-based Stimuli Generation in SystemC Verification Library (Wille et al., 2009) Automatic Constraint Generation for Guided Random Simulation (Yeh & Huang, 2010) Shuo Yang Robert Wille Daniel Große Rolf Drechsler University of Bremen DFKI GmbH solvertec GmbH SystemC Verification Library Problem Encoding for SAT
03
Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

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Chisel ARM V4 ISA ARMChisel Random Instruction Generator Functional Verification Coverage-Driven Verification Direct Test Verification FPGA Acceleration Test Stimulus Generation Processor Model Verification RTL Verilog Instruction Set Architecture Research on functional verification method processor model built by Chisel Lening WU Miao WANG Fu CHEN AVIC Xi'an Aeronautics Computing Technique Research Institute Northwestern Polytechnical University
04
ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard

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ConfigDrivenV Universal Verification Methodology (UVM) Constrained Random Test Generation Golden Reference Model Self-Checking Scoreboard RTL Verification Python-UVM Co-Verification 16-bit RISC Processor UART Controller SystemVerilog Python ModelSim Intel FPGA Starter Edition Bug Injection Functional Verification Coverage-Driven Verification File I/O Bridge (Python to UVM via $fscanf) Two-Layer Verification Architecture RISC-V Instruction Set Verification Formal Verification simple_cpu.v uart_tx.v uart_rx.v cpu_scoreboard.sv cpu_test.sv simple_cpu_buggy.v Mahatma Jyotiba Phule Rohilkhand University Accellera Systems Initiative ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard Vatsal Verma Unnati Gangwar Anuj Shakya Lalita Chauhan Janak Kapoor TLM Analysis Ports 8N1 Serial Framing Random Instruction Sequence Generation Cycle-Accurate Simulation
01
Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination

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87 ent archive
LiFU CPU Fuzzing Smart Coordination Feedback-Driven Coordination Semantic Seed Triage Hybrid Mutation LLM-Guided Generative Mutation Differential Testing Asymmetric Simulation ISS Pre-Run Filtering Reachability Analysis LLM-Guided Property Generation Coverage-Guided Fuzzing Formal Verification RTL Simulation Weight Cache Seed Scoring Pipelined Fuzzing Ensemble Fuzzing Random Mutation Directed Fuzzing Dependency Chain Generation Corpus Merging Assembly Synthesis SVA Property Synthesis Grey-Box Fuzzing White-Box Fuzzing Multi-Armed Bandit RFUZZ DirectFuzz DifuzzRTL Cascade HyPFuzz GenHuzz ProcessorFuzz WhisperFuzz TheHuzz ChatFuzz RISCV-Torture Spike VCS VC Formal GPT-4-turbo Instruction Set Simulator (ISS) Micro-Architectural State Space Coverage Feedback FSM Coverage Line Coverage Condition Coverage Seed Corpus Pipeline Hazard Data Forwarding Register Dependency Large Language Model (LLM) RTL RISC-V Mismatch Detection Testcase Generation Non-Progressing Testcase Filtering Knowledge Base Instruction Diversity Poisonous Interaction Coverpoint UVM Human-in-the-Loop Triage Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination Yuchen Hu Jialin Sun Yushu Du Renshuang Jiang Ning Wang Weiwei Shan Xinwei Fang Xi Wang Nan Guan Zhe Jiang Southeast University National Center of Technology Innovation for EDA National University of Defense Technology City University of Hong Kong University of York RocketChip BOOM CVA6 Algorithm 1: Filter for Non-Progressing Testcases Algorithm 2: Reachability Analysis for Uncovered Point Algorithm 3: LLM-Guided Property Generation Non-Progressing Testcase Filtering
02
Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior

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Spike Sail-RISC-V RVVTS RISC-V Vector Extension golden reference model positive testing negative testing coverage-guided test generation single instruction isolation failure code minimization ISA simulator executable specification formal specification functional coverage invalid instruction sequences valid instruction sequences machine state data-level parallelism riscvOVPsim RISCV-DV RISC-V Vector Tests Generator Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior Single Instruction Isolation for RISC-V Vector Test Failures Randomized Testing of RISC-V CPUs Using Direct Instruction Injection Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side Manfred Schlägl Katharina Ruep Daniel Große Vladimir Herdt Rolf Drechsler Alexandre Joannou Johannes Kepler University Linz Design Under Test instruction validity checking vector register grouping saturation flag architectural validation
03
IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application

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33 ent archive
Constrained Random Test Generation Converged Branch Instruction Stream Branch-Not-Taken (BNT) Mechanism Built-In Exception Handling Mechanism Deterministic Return from Interrupt Handler Mandatory Read-Only Registers Global Class Restriction Mechanism Machine State Detection and Restoration Mechanism Random Program Loop Generation Relocatable Interrupt Handler Address Translation Exception Handling Processor Pre-Silicon Functional Verification IBM GenesysPro Constrained Random Test Generator RAVEN Test Program Generator Test Generator 110 Program Loop in Processor Verification Early Exit from Loop Storage Addressability Preservation Speculative Execution Verification Branch History Table Verification Reentrant Mode Test Generation Test Case Definition Predefined Test Definition Generation Directive International Business Machines Corporation Functional Verification of the IBM System z10 Processor Chipset Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification Reconfigurable Model-Based Test Program Generator for Microprocessors IBM z/Architecture Addressing Mode (SAM24/SAM31/SAM64) Computer Program Product for Random Loop Test Generation Olaf K. Hendrickson Processor Pre-Silicon Functional Verification
04
WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors

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51 ent archive
WhisperFuzz white-box fuzzing black-box fuzzing grey-box fuzzing hardware fuzzing Micro-Event Graph register-transfer level timing side-channel attack timing vulnerability microarchitectural state transition finite-state machine coverage-feedback fuzzing seed generation differential testing operand mutation Micro-Event Path static program analysis SystemVerilog Assertion instruction sequence generation simulation trace hierarchical leakage analysis performance counter timing coverage metric speculative execution vulnerability information-flow tracking formal verification design-under-test Zkt extension HyPFuzz VCS Chipyard RISC-V ISA BOOM Rocket Core CVA6 Pallavi Borkar Chen Chen Mohamadreza Rostami Nikhilesh Singh Rahul Kande Ahmad-Reza Sadeghi Chester Rebeiro Jeyavijayan Rajendran Indian Institute of Technology Madras Texas A&M University Technische Universität Darmstadt WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors DIVUW instruction REMW instruction cache timing behavior breadth-first search
01
Generation of various programs in Verilog/SystemVerilog for testing EDA tools

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33 ent archive
ChiGen Verismith VlogHammer TransFuzz Verible Verilator Yosys Jasper Formal Verification Platform Icarus Verilog ChiBench Fuzzing Probabilistic Grammar Hardware Description Language Verilog SystemVerilog SystemVerilog Assertions Formal Verification Electronic Design Automation n-gram Language Model Hindley-Milner Type Inference Scope Management Abstract Syntax Tree Generation Packages (SystemVerilog) Interfaces (SystemVerilog) Classes (SystemVerilog) Large Language Model Luiza de Melo Gomes Fernando Magno Quintão Pereira UFMG Cadence Design Systems RTL Benchmark Suite Generation of various programs in Verilog/SystemVerilog for testing EDA tools
02
Bottom-Up Generation of Verilog Designs for Testing EDA Tools

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34 ent archive
ChiGen Verismith VlogHammer TransFuzz Yosys Verilator Verible Jasper Formal Verification Platform Icarus Verilog Fuzzing Bottom-Up Generation Probabilistic Context-Free Grammar Hindley-Milner Type Inference Code Injection Reaching Definition Analysis Variable Renaming and Scope Creation Verilog SystemVerilog Hardware Description Language Electronic Design Automation RTL ChiBench Constraint Generation and Unification Abstract Syntax Tree Skeleton Generation Cadence Design Systems UFMG Fernando Magno Quintão Pereira Code Coverage Context-Sensitive Probabilities Module Injection Lost in Translation: Enabling Confused Deputy Attacks on EDA Software with TransFuzz A General Framework for Hindley/Milner Type Systems with Constraints AddressSanitizer
03
Search+LLM-Based Testing for ARM Simulators

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42 ent archive
SearchSYS gem5 AFL++ Differential Testing LLM-based Test Code Generation Coverage-Guided Fuzz Testing Zero-Shot Prompting Search-Based Software Testing Seed Generation Parameterized Input Generation Mutation Operators Prompt Engineering ARM Instruction Set Architecture X86 Instruction Set Architecture RISC-V ARMv8 GPT-3.5-turbo CodeLlama TinyLlama Phi2 Llama2 Magicoder CodeBooga Ollama C Token Categories for Prompt Templates Binary File Mutation Compiler Optimization Tokens Search+LLM-based Testing for ARM Simulators Karine Even-Mendoza Héctor D. Menéndez W.B. Langdon Aidan Dakhama Justyna Petke Bobby R. Bruce King's College London University College London University of California, Davis ARM Regression Testing Test Suite Minimization afl-cmin C Program Generation
02
riscv/riscv-opcodes

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35 ent archive
RISC-V Opcodes Repository RISC-V instruction opcodes RISC-V control and status registers instruction encoding regular instruction pseudo-op instruction imported instruction opcode bit encoding mask match variable fields unratified extension canonical ordering encoding.h parse.py instr_dict.json instr-table.tex priv-instr-table.tex inst.chisel inst.sverilog inst.rs inst.spinalhdl inst.go Spike PK uv RISC-V Manual RISC-V rv32 rv64 RISC-V I extension RISC-V M extension artifact generation instr_dict
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riscv-verification/RVVI

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RISC-V Verification Interface (RVVI) RVVI-TRACE RVVI-TEXT RVVI-API RVVI-VVP RISC-V Formal Interface (RVFI) Hardware Design Verification (HW DV) RTL test bench reference model functional coverage stimulus generation virtual verification peripherals asynchronous interrupts Out-of-Order execution multi-hart SystemVerilog DPI instruction set simulator (ISS) ImperasDV Verilator Xcelium VCS Questa Imperas EMMicro SiLabs OpenHW Group SymbioticEDA Synopsys Cadence Siemens EDA CV32E40X core-v-verif
06
Towards Efficient and Automated Side Channel Evaluations at Design Time

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61 ent archive
CASCADE Side Channel Analysis Simple Power Analysis Differential Power Analysis Correlation Power Analysis Mutual Information Analysis Test Vector Leakage Assessment Exhaustive Dynamic Power Capturing Marching-Sticks Model Hamming Distance Model Instantaneous Power Consumption Simulation Composite Current Source Models Delta-Delay Model Zero-Delay Model SPICE Simulation Standard-Cell Design Flow Threshold Implementation Wave Dynamic Differential Logic Domain-Oriented Masking Masking Logic Simulation Physical Simulation Test Bench Generation Pseudo-Random Input Sequence Generation Fixed vs. Random TVLA Welch's T-Test Higher-Order Statistical Moment Analysis Measurement to Disclosure Instantaneous Power Consumption Power Frame File Analyzed Frame Data Standard Delay Format Open Liberty Format Pre-Silicon Evaluation Simulation Frame Synopsys Design Compiler Cadence Innovus MentorGraphics QuestaSim Synopsys PrimeTime PX Synopsys HSPICE Test Bench Generator Delay Generator SPICE Generator Logic Parser Power Parser SPICE Parser Session Manager Library Manager TVLA Analyzer AES-128 Unrolled Implementation TI PRESENT S-Box WDDL PRESENT S-Layer Danilo Sijacic Josep Balasch Bohan Yang Santosh Ghosh Ingrid Verbauwhede imec-COSIC KU Leuven Intel Labs Towards Efficient and Automated Side Channel Evaluations at Design Time Synopsys PrimeTime PX
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Feedback-based Coverage Directed Test Generation: An industrial evaluation

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Coverage Directed test Generation MicroGP Genetic Programming Evolutionary Algorithm Genetic Algorithm Instruction Set Architecture Code Coverage RTL FireDrill FirePath Instruction Library Fitness Function Pseudo-random Test Generation Regression Test Suite Branch Coverage Toggle Coverage Expression Coverage Functional Coverage Machine Learning SIMD Charalambos Ioannides Geoff Barrett Kerstin Eder G. Squillero Broadcom Corporation University of Bristol Polytechnic University of Torino Feedback-based Coverage Directed Test Generation: An industrial evaluation simulate_e.pl postprocess.pl ugp_fd.e Microprocessor Verification Test Program Generation Mutation Operator Crossover Operator Coverage Closure Coverage Directed test Generation
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FISH: Fast Instruction SyntHesis for Custom Processors

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41 ent archive
FISH (Fast Instruction SyntHesis) Maximal Convex Subgraph Enumeration Integer Linear Programming (ILP) for Custom Instruction Synthesis Data Flow Graph (DFG) Custom Instruction Synthesis Custom Instruction Candidate Convex Subgraph Forbidden Node Graph Compaction and Clustering Search Tree with Constraint Propagation Merit Function for Subgraph Evaluation Trimaran Compiler CHIPS Tool Chain Synopsys Design Compiler Design Space Exploration Custom Processor System-on-Chip (SoC) Register File Port Constraint Incompatibility Graph Software Execution Latency Estimation Hardware Execution Latency Estimation VHDL Behavioral Hardware Description Generation If-Conversion Pass Subgraph Selection CPLEX ILP Solver lp_solve ILP Solver Bron-Kerbosch Maximal Clique Enumeration Pothineni et al. Maximal Convex Subgraph Enumeration Verma et al. Maximal Clique Enumeration for Custom Instructions Li et al. Search Tree Enumeration Algorithm Kubilay Atasu Wayne Luk Oskar Mencer Can Özturan Günhan Dündar IBM Research Zurich Imperial College London Boğaziçi University Advanced Encryption Standard (AES) Benchmark Data Encryption Standard (DES) Benchmark Multimedia and Cryptography Benchmarks
01
Defining macros - RISC-V Formal documentation

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24 ent archive
riscv-formal genchecks.py RVFI RISC-V Compressed ISA fused instructions formal verification bounded model checking unbounded model checking liveness checking blackbox register file blackbox ALU word-aligned memory access Physical Memory Attributes (PMA) Control and Status Registers (CSRs) WFI instruction U-mode S-mode Yosys simulation rvfi_macros.vh assume_stmts.vh rvformal_rand_reg rvformal_rand_const_reg RISC-V
02
Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV

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36 ent archive
Prabhat Mishra Nikil Dutt Center for Embedded Computer Systems, University of California, Irvine Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV functional test program generation model checking Architecture Description Language SMV model checker pipelined processor microprocessor verification formal verification EXPRESSION ADL DLX processor counterexample generation pipeline hazard functional coverage coverage estimation pipeline path data-transfer path cycle-accurate structural simulator RTL description SAT-based bounded model checking processor model instruction set architecture simulation-based verification branch prediction feedback path read-after-write hazard SMV language SMV description of DLX architecture Sandeep Shukla Motorola Inc. Hitachi Ltd. PowerPC processor FSM-based processor modeling controllability problem
03
A methodology for processor implementation verification | Springer Nature Link

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77 ent archive
Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator A. Aharon A. Bar-David B. Dorfman E. Gofman M. Leibowitz V. Shwartzbund Dynamic Biased Pseudo-Random Test Program Generation IBM RISC System/6000 The Pentium Bug, an Industry Watershed B. Beizer Test Program Generation for Functional Verification of PowerPC Processors in IBM D. Goodman M. Levinger Y. Lichtenstein Y. Malka C. Metzger M. Molco G. Shurek Test Program Generation for Functional Verification Model Based Test Generation for Processor Design Verification Model-Based Test Generation Design Verification of the HP9000 Series 7000 PA-RISC Workstations AVPGEN — A Test Case Generator for Architecture Verification AVPGEN A. Chandra V. Iyengar D. Jameson R. Jawalker I. Nair B. Rosen D. Geist Y. Wolfstal Partition Testing Analyzing Partition Testing Strategies Theories of Program Testing and the Application of Revealing Subdomains E. J. Weyuker T. J. Ostrand Coverage Driven Processor Bug Classification Y. Abarbanel S. Ur Coverage-Driven Verification Design and Validation of Computer Protocols G. J. Holtzman Symbolic Model Checking K. L. McMillan The SMV System DRAFT SMV Symbolic Model Checking Architectural Verification of Processors Using Symbolic Instruction Graphs Symbolic Instruction Graphs Constraint Satisfaction for Test Program Generation D. Lewin L. Fournier E. Roytman Constraint Satisfaction for Test Program Generation Architecture Validation for Processors Automatic Test Program Generation for Pipelined Processors H. Iwashita S. Kowatari T. Nakata F. Hirose Automatic Test Program Generation for Pipelined Processors Formally Verifying a Microprocessor Using a Simulation Methodology D. L. Beatty R. E. Bryant Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures T. A. Diep J. P. Shen Integrated Design and Test Assistance for Pipeline Controllers The PowerPC Architecture POWER and PowerPC A Processor Implementation Verification Methodology D. Lorenz IBM Hewlett-Packard Carnegie Mellon University
01
Fuzzing - Awesome List

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31 ent archive
DifuzzRTL MorFuzz SpecFuzz Transynther Cascade GenHuzz DiveFuzz RVISmith DIFUZZRTL: Differential Fuzz Testing to Find CPU Bugs MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation Cascade: CPU Fuzzing via Intricate Program Generation GenHuzz: An Efficient Generative Hardware Fuzzer DiveFuzz: Enhancing CPU Fuzzing via Diverse Instruction Construction RVISmith: Fuzzing Compilers for RVV Intrinsics Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities SpecDoctor: Differential Fuzz Testing to Find Transient Execution Vulnerabilities SpecFuzz: Bringing Spectre-type vulnerabilities to the surface differential fuzz testing for CPU verification golden-reference model fuzzing runtime instruction morphing intricate program generation for CPU fuzzing diverse instruction construction co-simulation for processor fuzzing CPU fuzzing RTL RISC-V transient execution vulnerabilities Spectre vulnerabilities Meltdown attacks microcode assists RVV intrinsics
02
Recent Papers Related To Fuzzing | FuzzingPaper

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SpecDoctor DifuzzRTL RTL Fuzzing Register Coverage Transient Execution Vulnerability Differential Fuzzing ISA Simulation CPU Verification Instruction Generation Fuzzing Template Multi-phased Fuzzing Cross-checking Coverage-guided Greybox Fuzzing RISC-V CPU BOOM (RISC-V CPU) NutShell-Argo CPU Side-channel Attack Spectre Meltdown ForeShadow RTL Design ISA Instruction Mutation DifuzzRTL: Differential Fuzz Testing to Find CPU Bug (S&P 2021) SpecDoctor: Differential Fuzz Testing to Find Transient Execution Vulnerabilities
03
Structured Random Differential Testing of Instruction Decoders

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46 ent archive
Structured Random Differential Testing of Instruction Decoders Nathan Jay Barton P. Miller University of Wisconsin Fleece XED libopcodes LLVM Dyninst Capstone instruction decoder differential testing structured random testing instruction structure inference bit flipping mutation reassembly-based output verification model-based input generation grammar-based input generation CPU execution for valid input generation instruction set architecture x86 architecture ARM architecture PowerPC architecture opcode encoding EVEX prefix REX prefix VEX prefix binary executable analysis control flow graph format string deduplication pairwise structural bit flips field randomization special operand values Paleari et al. 2010 x86 decoder differential testing DERIVE system GNU assembler seed byte string instruction length detection reserved bit structural bit field bit unused bit output normalization error reporting Seidel 3DNow! extension
04
Efficient State Space Exploration: Interleaving Stateless and State-based Model Checking

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Efficient State Space Exploration: Interleaving Stateless and State-based Model Checking Malay K. Ganai Chao Wang Weihong Li NEC Laboratories America HMC (Hybrid Model Checker) State-based Model Checking Stateless Model Checking Bounded Model Checking (BMC) SMT-based Bounded Model Checking Presburger Arithmetic-based Symbolic Traversal State Decomposition State Prioritization Divide-and-Conquer Strategy Reachability Properties Frontier States Extended Finite State Machine (EFSM) Control Flow Graph (CFG) Satisfiability Modulo Theory (SMT) Presburger Arithmetic Disjunctive Normal Form (DNF) Image Computation Control State Reachability (CSR) State Traversal (ST) Path-based Reasoning (PR) Binary Decision Diagrams (BDDs) Linear Integer Arithmetic (LIA) Unbounded Model Checking Symbolic State Traversal State Disjunct Unreachable Block Constraint (UBC) Goal-directed Lighthouses (glh) Deep-state Prioritization (dfs) BMC Completeness Threshold Over-approximated Pre-image Operator Embedded Software Verification Program Slicing Constant Value Propagation Yices SMT Solver CUDD Library Omega Library Polyhedral Representation Fixpoint Computation Memory Bound Transition Relation SAT-based Model Checking Interpolant-based Approach State Partitioning Data Parallelism LTL Property
05
Adding Physical Memory Protection to the VeeR EL2 RISC ...

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44 ent archive
Antmicro CHIPS Alliance Google AMD NVIDIA Microsoft RISC-V International COMSEC ETH Zürich Caliptra Root of Trust Physical Memory Protection (PMP) RISC-V Control and Status Registers (CSR) Address Matching Naturally Aligned Power-of-2 (NAPOT) Naturally Aligned Four-byte (NA4) Top of Range (TOR) Lock Bit Mechanism XWR Permissions Universal Verification Methodology (UVM) RTL Device Under Test (DUT) Instruction Cache Program Counter Trap Handler CPU Fuzzing Continuous Integration (CI) Functional Testing Coverage Testing Randomized Stimulus Generation Scoreboard-based Verification Reference Prediction Model pyUVM Verilator RISCOF riscv-dv Cascade VeeR EL2 Core PMP Module RTL Implementation xwr_access Test Region Boundaries Sequence Configuration Sequence Software Execution Test (pmp/main.c) Region Boundaries Sequence