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riscv-dv
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+174 entities · +228 links — latest run (2026-06-09)
activity
01
Testbench Automation and Constraints Tutorial - Doulos

Processed 30 entities and 36 relations.

30 ent archive
Directed-Random Verification Directed Testing Random Testing Constrained-Random Stimulus Generation Functional Coverage Corner Case Testing Transaction-Level Modeling Design Under Test Constraints Pseudo-Random Stimulus Generation Stimulus Serialization Coverage-Driven Verification Covergroup Coverpoint Cross Coverage Coverage Bins Transition Coverage Illegal Bins Class-Based Testbench CAN_Message class message_t struct randomize() method getbits task set_RTR task CANbus Protocol Dynamic Array SystemVerilog Constrained-Random Testbench pre_randomize and post_randomize callbacks Assertion-Based Verification Doulos
02
Destroying x86_64 instruction decoders with differential fuzzing - The Trail of Bits Blog

Processed 29 entities and 36 relations.

29 ent archive
Mishegos differential fuzzing sliding mutation engine x86_64 instruction decoding x86_64 instruction format variable-length instruction encoding instruction candidate generation ModR/M byte SIB byte instruction prefix window-based fuzzing cohort output shared memory slot worker process ABI Capstone libbfd XED Zydis mishmat analysis pass analysis filter decoder discrepancy adversarial instruction sequence disassembly RISC ISA Trail of Bits mishegos worker passes.yml input minimization
03
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation - Lund University

Processed 16 entities and 21 relations.

16 ent archive
IFPEC Constraint Programming Processor Extensions Custom Instructions Subgraph Isomorphism Application Compilation Runtime Reconfigurable Cells Application Scheduling Reconfigurable Processor Graph Representation Kevin Martin Christophe Wolinski Krzysztof Kuchcinski Antoine Floch Francois Charot Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
04
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models

Processed 41 entities and 60 relations.

41 ent archive
Instruction Set Simulator Instruction Set Architecture Virtual Prototype Formal ISA Model RISC-V LIBRISCV Embedded Domain-Specific Language Spike RISC-V VP Interface Model ISS Code Generation Instruction Execution Unit Instruction Semantics Fetch-Decode-Execute Cycle Instruction Decoding SystemC Sail GRIFT Forvis Kami DSL language-c Abstract Syntax Tree Free Monads Register File Memory Interface Embench Benchmark Suite RISC-V ISA Tests Architecture Description Language Minimally Invasive ISS Generation Simulator-Agnostic Code Generation Sören Tempel Tobias Brandt Christoph Lüth Rolf Drechsler University of Bremen DFKI GmbH Virtual Prototyping Haskell Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models formal-iss code generation tool University of Bremen
05
Arslan, Mehmet Ali

Processed 58 entities and 75 relations.

58 ent archive
Mehmet Ali Arslan Lund University Code Generation for Custom Architectures using Constraint Programming Constraint Programming Code Generation Instruction Selection Instruction Scheduling Register Allocation Data Assignment Modulo Scheduling Pipelined Execution Single Instruction Multiple Data Multi-bank Memory Intermediate Representation Instruction Level Parallelism Data Parallelism Vectorization Loop Unrolling Bank Conflict Graph Coloring Global Constraints Cumulative Global Constraint Non-overlapping Rectangles Pareto Points Superblock Instruction Scheduling Permutation Vector Optimization Polyhedral Compilation Macro-SIMDization Micro-SIMDization Domain Specific Language Branch-and-Bound Integer Linear Programming Dynamic Programming Subgraph Isomorphism Directed Acyclic Graph Coarse-Grained Reconfigurable Architecture Very Large Instruction Word Digital Signal Processing Embedded Systems Application-Set Driven Architecture Exploration JaCoP Unison ePUMA Architecture EIT Architecture Matrix Processing Element Inverse Discrete Cosine Transformation Krzysztof Kuchcinski Flavius Gruian Jörn W. Janneck Pierre Flener Chaitin Lifetime Analysis Diff2 Global Constraint Search Space Heuristics Stream Graph Scheduling Scalar Register File Vector Register File Pipelined Execution
01
[PDF] ProcessorFuzz: Processor Fuzzing with Control and Status ...

Processed 61 entities and 63 relations.

61 ent archive
ProcessorFuzz DIFUZZRTL Coverage-based Greybox Fuzzing CSR-transition coverage register coverage differential testing ISA simulation RTL simulation multiplexer toggle coverage random instruction generation coverage-directed test generation Control and Status Registers Finite State Machine seed corpus mutation engine Transition Map Transition Unit extended ISA trace log assembly program test inputs pre-silicon verification hardware fuzzing Register-Transfer Level ISA specification privilege mode Time-to-Exposure Spike ISA simulator Verilator Dromajo RFUZZ TheHuzz Cadence ModelSim Rocket Chip SoC Generator Rocket Core BOOM Core BlackParrot Core RISC-V Hardware Description Language Chisel HDL SystemVerilog HDL MulDiv module remainder register mstatus CSR fflags CSR mcause CSR medeleg CSR instret CSR sepc CSR Physical Memory Protection page table formal verification Boston University University of Washington Sadullah Canakci Chathura Rajapaksha Leila Delshadtehrani Anoop Nataraja Michael Bedford Taylor Manuel Egele Ajay Joshi ProcessorFuzz paper
02
[PDF] UCAM-CL-TR-984.pdf

Processed 54 entities and 94 relations.

54 ent archive
CHERI RISC-V TestRIG QuickCheckVEngine RVFI-DII Piccolo Flute Toooba RiscyOO Bluespec spatial memory safety temporal memory safety sweeping revocation capability hardware security superscalar out-of-order processor merged register file FPGA prototyping Direct Instruction Injection Physical Memory Protection Memory Management Unit Program Counter Capability tag controller CHERI Capability Library Sail CHERI-RISC-V BlueStuff CHERI-Concentrate Sentry mechanism CHERIvoke microcontroller RISC-V Formal Interface bounds checking instruction pipeline UCAM-CL-TR-984 Peter David Rugg University of Cambridge Computer Laboratory DARPA Instruction Set Architecture Return-Oriented Programming capability mode bit safe speculation shadow bitmap MiBench CoreMark SPEC Vivado MIPS architecture Morello linear capabilities indirect capabilities prefetching virtual memory cache coherence RISC-V BOOM Memory Protection Unit
03
Achim D. Brucker - brucker.ea-test-program-generation-2013

Processed 19 entities and 22 relations.

19 ent archive
Test Program Generation for a Microprocessor: A Case-Study Achim D. Brucker Abderrahmane Feliachi Yakoub Nemouchi Burkhart Wolff Test Program Generation Symbolic Test Case Generation Black Box Testing White Box Testing Model-Based Testing Conformance Test Scenarios Formal Microprocessor Model Instruction Set Verification Hardware-in-the-Loop Testing Common Criteria EAL 7 Theorem Proving HOL-TestGen Isabelle/HOL Springer-Verlag
04
Automated Formal Verification of Processors

Processed 43 entities and 61 relations.

43 ent archive
FISACO OneSpin 360 MV Interval Property Checking Bounded Model Checking Completeness Analysis Automatic Property Generation k-induction SAT-based Formal Verification Pipeline Modeling Data Path Modeling Architecture Description Mapping Functions Consistency Assertions Instruction Set Simulator Generation Theorem Proving Register Transfer Level Instruction Set Architecture Property Suite Multicycle Instructions Pipeline Hazards Branch Prediction Exceptions and Interrupts Register Forwarding Finite State Machine Safety Properties Transaction Level Model Design Under Verification Simulation-Based Verification Invariant Generation Advanced Automation in Formal Verification of Processors Ulrich Kühne Sven Beyer Jörg Bormann John Barstow OneSpin Solutions GmbH Infineon Technologies University of Bremen LSV ENS de Cachan LISA Facile Peripheral Control Processor Interface Transactions Architecture Description Language
05
[PDF] Verifying Instruction Set Simulators using Coverage-guided Fuzzing

Processed 40 entities and 48 relations.

40 ent archive
Instruction Set Simulator Coverage-guided Fuzzing libFuzzer AFL RISC-V Spike Forvis RISC-V Virtual Prototype RISC-V Torture Test Generator RISC-V ISA Tests Functional Coverage Code Coverage Mutation-based Fuzzing Model-based Test Generation Instruction Set Architecture Constrained Random Verification ELF Binary Branch Coverage Custom Mutation Procedure Instruction Sequence Control and Status Register Illegal Instruction Handling Simulation-based Verification Vladimir Herdt Daniel Große Hoang M. Le Rolf Drechsler University of Bremen DFKI GmbH Verifying Instruction Set Simulators using Coverage-guided Fuzzing Dynamic Program Analysis SMT Solver Bayesian Network Test Generation Machine Learning for Fuzzing RV32IMA Instruction Decoder Register File In-process Fuzzing LLVMFuzzerTestOneInput Coverage-guided Fuzzing
01
Verification procedure - RISC-V Formal documentation

Processed 30 entities and 44 relations.

30 ent archive
riscv-formal genchecks.py insns/generate.py RVFI RISC-V ISA compliance verification Bounded Model Check unbounded verification smtbmc boolector rv32i rv64i instruction check PC check causality check liveness check uniqueness check cover check CSR check memory abstraction bus memcheck instruction memcheck data memcheck rvfi_testbench.sv cover_stmts.vh checks.cfg RTL faults check blackbox SystemVerilog
02
Who tests the TestRIG? Tooling for randomised tandem verification

Processed 32 entities and 40 relations.

32 ent archive
TestRIG Randomised Tandem Verification RVFI-DII QuickCheckVEngine QuickCheck Sail RISC-V CHERI Toooba CVA6 Mutation-Based Testing Mutation Adequacy Counterexample Shrinking Directed Random Verification Static Test Suite Generation Fuzzing RTL SQLite Peter Rugg Alexandre Joannou Jonathan Woodruff Franz A. Fuchs Simon W. Moore University of Cambridge Microsoft Research lowRISC SCI Semiconductor Who tests the TestRIG? Tooling for randomised tandem verification Branch Prediction Lockup Bug Detection RISC-V Compressed Instructions Mutation Adequacy
01
[PDF] MorFuzz: Fuzzing Processor via Runtime Instruction Morphing ...

Processed 54 entities and 76 relations.

54 ent archive
MorFuzz Instruction Morphing Stimulus Template Synchronizable Co-simulation State Synchronization Field Level Mutation Semantic Level Mutation Instruction Shuffle Coverage-Guided Fuzzing Runtime Instruction Morphing Magic Instruction Generation Constrained Random Instruction Generation Static Formal Verification Simulation-Based Verification RTL Simulation Processor Fuzzing RISC-V ISA Co-simulation Control Register Coverage Fuzzing Execution Environment Fuzzing Payload Morpher Testing Block Watchpoint Instruction Golden Reference Model Implementation Differences Sequence Pattern Type Pool Morphing Map DifuzzRTL TheHuzz riscv-dv riscv-torture spike Synopsys VCS starship SoC generator FIRRTL CVA6 Rocket BOOM MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation Jinyan Xu Yiyuan Liu Sirui He Haoran Lin Yajin Zhou Cong Wang Zhejiang University City University of Hong Kong UC Berkeley Instruction Stream Generation Hardware Bug Detection Mux Coverage Hardware Behavior Coverage
02
DiffTest-H: Toward Semantic-Aware Communication in Hardware-Accelerated Processor Verification

Processed 59 entities and 68 relations.

59 ent archive
DiffTest-H Kunlin You Yinan Xu Kehan Feng Luoshan Cai Yaoyang Zhou Yungang Bao State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences Beijing Institute of Open Source Chip co-simulation design under test (DUT) golden reference model (REF) non-deterministic events (NDEs) verification events communication overhead hardware-software communication structural semantics order semantics behavioral semantics instruction-level debuggability Batch (tight packing of verification events) Squash (order-decoupled fusion) Replay (lightweight debugging by event retransmission) event fusion hardware-software parallelism (non-blocking transmission) differencing (event field delta compression) multi-level packing strategy LogGP model DiffTest XiangShan NutShell Verilator Synopsys VCS Spike (ISS) NEMU Cadence Palladium Xilinx VU19P FPGA Fromajo RISC-V RTL simulation FPGA prototyping hardware emulation DPI-C interface instruction commit register update memory access (MMIO) cache coherence verification TLB operations ISA checker monitor unit token-based management (replay tokens) snapshot debugging compensation-based REF revert Chisel HDL XDMA protocol GFIFO (emulator non-blocking primitive) DUT trace dumping and reloading out-of-order processor vector/hypervisor extensions
04
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

Processed 63 entities and 90 relations.

63 ent archive
Tandem Simulation RTL Co-simulation Instruction Set Architecture (ISA) Instruction-Level Abstraction (ILA) Instruction-Level Execution Model (ILEM) RTL-Based Execution Model (RTEM) Cross-Level Execution Model (CLEM) Architectural Variable (AV) AV-Check AV-Swap Refinement Map Conformance Testing Jump-Starting (Warm-Up Simulation) Checkpoint Map Instruction Map AV Map Cold Start Micro-Architectural Variables Simulation-Based Testing RTL (Register Transfer Level) RISC-V Memory-Mapped Input/Output (MMIO) Testbench Instruction-by-Instruction Checking System-on-Chip (SoC) High-Level Synthesis (HLS) Transaction-Level Model (TLM) Decode Function State Update Function Child-ILA (Child Instructions) ILAtor ILAng Verilator Tandem Generator AV-Comparator AV-Converter Instruction Monitor Dromajo RISC-V ISA Co-simulator Bluespec System Verilog Chisel Halide SystemC AES ILA Model AES-RTL (Block Implementation) AES-RTL (Round Implementation) GaussianBlur RTL FlexNLP RTL PicoRV32 (Pico) Piccolo RISC-V Core Rocket Core RISC-V ILA Model Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models Yue Xing Aarti Gupta Sharad Malik Princeton University DARPA Esperanto Technology Bug Detection Formal Verification Test Stimulus Generation Random Test Input Generation Program Counter (Auxiliary for Accelerator)
01
RVDFI: A RISC-V Architecture with Security

Processed 41 entities and 49 relations.

41 ent archive
RVDFI Data-Flow Integrity RISC-V Rocket Chip Reaching Definition Set Reaching Definition Table RoCC Static Analysis LLVM SVF Andersen's Algorithm Instruction Instrumentation custom0 instruction DFI Verification Flow DFI Controller DFI-Request FIFO Dynamic Redundant Load Pruning Load Pruning Buffer Dedicated DFI Cache Function Return Protection Library Protection Control-Flow Integrity Write Integrity Testing HDFI TMDFI PIM-DFI Near-Memory Processing RTL SPEC CPU2006 RDSmap Target Address Buffer Miss Status Holding Registers Lang Feng Jiayi Huang Luyi Li Haochen Zhang Zhongfeng Wang Return-Oriented Programming Jump-Oriented Programming ISA Extension Processor Pipeline
01
Applying Constrained-Random Verification to Microprocessors - EE Times

Processed 31 entities and 27 relations.

31 ent archive
Constrained-Random Verification Directed Random Stimulus Directed Stimulus Object-Oriented Stimulus Generation Top-Down Stimulus Planning Transaction Abstraction Instruction Scenario Generation Branch Scenario Constraint Modeling Exception Condition Stimulus Planning Random Sequence Generation SystemVerilog SystemVerilog Random Sequence Generator VMM Synopsys Program Trace Instruction Scenario Opcode Class Instruction Set Architecture MIPS-I Instruction Set Scenario Generator Processor Testbench Design Under Test Illegal Opcode Exception Memory Alignment Exception Forward Branch Backward Branch opcode::psdisplay() opcode::byte_pack() Chun-hsiang Chang Andreas Kuehlmann Arteris
02
Generating AMD microcode stimuli using VCS constraint solver

Processed 30 entities and 30 relations.

30 ent archive
Gregory Tang Rajat Bahl Alex Wakefield Padmaraj Ramachandran AMD, Inc. Synopsys Inc. hierarchical constrained-random test generation sequential randomization single-class randomization multi-class randomization constrained-random stimulus generation microcode test sequence generation opcode distribution and biasing corner case coverage instruction field randomization opcode category partitioning wrapper class architecture CPU opcode generation BDD solution space elaboration Synopsys VCS constraint solver VCS constraint profiler RACE solver BDD solver VCS 2009.12 SystemVerilog constraint language SystemVerilog random sequence construct object-oriented verification methodology weighted knobs for test control testcase extraction feature op_gen.sv
03
Optimizing Design Verification using Machine Learning: Doing better than Random

Processed 18 entities and 18 relations.

18 ent archive
Design Verification Constrained Random Stimulus Functional Coverage Supervised Learning Reinforcement Learning Coverage Points Random Instruction Generation RISCV Random Instruction Generator Constrained Random DV Environment RISCV-Ariane Cache Controller Design RTL RISC-V Optimizing Design Verification using Machine Learning: Doing better than Random William Hughes Sandeep Srinivasan Google Machine Learning for Verification
2026-06-02
cecs.uci.edu/~papers
01
Code Generation and Analysis for the Functional Verification of Microprocessors

Processed 49 entities and 64 relations.

49 ent archive
functional verification code generation microprocessor RTL model pseudorandom code generation heuristic-based code generation self-checking code diagnostic program architectural simulator speculative execution cache coherency multiprocessor verification constraint solving instruction template Intermediate Code Representation register allocation Abstract Graph Description diagnostic database instruction histogram event coverage trace file simulation-based verification branch prediction pipeline bypass superscalar processor template placement algorithm user-assisted code generation post-processing trace analysis SBVer BRVer MPVer MPApplicationVerifier Theo Profiler Ans refdif streamer RTL simulator AVPGEN MTPG Code Generation and Analysis for the Functional Verification of Microprocessors Anoosh Hosseini Dimitrios Mavroidis Pavlos Konas Silicon Graphics Inc. SPLASH-2 benchmarks memory management unit external interface unit DVT team
02
Applying Constrained-Random Verification to Microprocessors - EE Times

Processed 26 entities and 31 relations.

26 ent archive
Constrained-Random Verification (CRV) Microprocessor Verification Stimulus Generation Top-Down Stimulus Planning Object-Oriented Verification SystemVerilog SystemVerilog Random Sequence Generator Verification Methodology Manual (VMM) Synopsys MIPS-I Instruction Set Architecture Instruction Scenario Program Trace Transaction Abstraction Opcode Class Instruction Class Common Instruction Scenario Base Class Scenario Generator Directed Random Stimulus Directed Test Exception Handling Verification Branch Scenario Generation Memory Alignment Constraint SystemVerilog foreach Array Constraints Design Under Test (DUT) Chun-hsiang Chang vmm_data
2026-05-31
opentitan.org/book
01
Random Instruction Generator - OpenTitan Documentation

Processed 22 entities and 21 relations.

22 ent archive
otbn-rig gen-binaries.py random instruction generator snippet straight-line instruction sequence conditional branch snippet loop snippet random seed program size bound architecturally unspecified behaviour avoidance randomly initialised data random program generation assembly generation from JSON JSON program representation assembly listing (.s file) linker script (.ld file) OTBN toolchain OTBN dmem register file test case mutation test case shrinking
01
Cross-Level Processor Verification via

Processed 49 entities and 48 relations.

49 ent archive
Register-Transfer Level (RTL) Randomized Instruction Stream Generation Coverage-guided Aging Cross-Level Processor Verification Instruction Set Simulator (ISS) Co-simulation Functional Coverage Endless Instruction Stream RISC-V Instruction Set Architecture Google RISC-V Design Verification (DV) Framework Constraint-based Test Generation Coverage-guided Fuzzing Instruction Injection Pipelined Processor Branch Prediction Control and Status Registers (CSRs) Simulation-based Verification Formal Verification Model-based Test Generation Bayesian Network Coverage-directed Test Generation Symbolic Execution Instruction Group Cross-product Coverage Points riscv-vp Verilator SystemC Coverage-Observer Instruction Generator (InstrGen) Core Adapter Comparator (RTL vs ISS) MINRES The Good Core (TGC) Genesys-Pro MicroTESK RISC-V Formal Verification Framework OneSpin 360 DV RISC-V Verification App Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging Niklas Bruns Vladimir Herdt Eyck Jentzsch Rolf Drechsler University of Bremen DFKI GmbH MINRES Technologies GmbH Google UC Berkeley Machine Learning for Test Generation RV32I Base Integer ISA Cryptographic Seed for Deterministic Randomness Google RISC-V Design Verification (DV) Framework Instruction Injection
02
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

Processed 20 entities and 19 relations.

20 ent archive
TurboFuzz hardware fuzzing processor verification agile verification FPGA-accelerated verification Test Generation-Simulation-Coverage Feedback loop coverage convergence test case generation seed control flow inter-seed scheduling hybrid fuzzer integration feedback-driven generation simulation-based verification instruction set architecture RISC-V FPGA ASIC TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification Yang Zhong Haoran Wu
03
Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

Processed 10 entities and 9 relations.

10 ent archive
Randal E. Bryant Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic Equality with Uninterpreted Functions (EUF) Propositional Logic Ordered Binary Decision Diagrams (BDDs) Boolean Satisfiability Checking Burch-Dill Verification Method Pipelined Processor Verification Maximally Diverse Interpretations Control Logic Abstraction
01
Verifying Instruction Set Simulators using Coverage-guided Fuzzing

Processed 35 entities and 42 relations.

35 ent archive
Verifying Instruction Set Simulators using Coverage-guided Fuzzing Vladimir Herdt Daniel Große Hoang M. Le Rolf Drechsler University of Bremen DFKI GmbH Instruction Set Simulator Coverage-guided Fuzzing RISC-V libFuzzer AFL Spike Forvis RISC-V Virtual Prototype Functional Coverage Code Coverage Mutation-based Fuzzing Model-based Test Generation Constrained Random Verification Instruction Set Architecture RISC-V Torture Test Generator RISC-V ISA Tests ELF Binary Differential Testing Branch Coverage Dynamic Program Analysis CSP/SMT Solver Machine Learning for Fuzzing Control and Status Registers LLVMFuzzerTestOneInput Instruction Decoder Bayesian Network Test Generation Processor Stimulus Generation Coverage-guided Fuzzing
02
ProcessorFuzz: Processor Fuzzing with Control and

Processed 60 entities and 85 relations.

60 ent archive
ProcessorFuzz CSR-transition coverage DIFUZZRTL Coverage-based Greybox Fuzzing register coverage differential testing hardware fuzzing software fuzzing Control and Status Registers Register-Transfer Level ISA simulation Finite State Machine multiplexer toggle coverage seed corpus mutation engine Transition Unit Transition Map extended ISA trace log random instruction generation coverage-directed test generation assembly program test input Time-to-Exposure Spike ISA simulator Verilator Dromajo RFUZZ TheHuzz RISC-V ISA Rocket Core BOOM Core BlackParrot Core Rocket Chip SoC Generator Chisel HDL SystemVerilog HDL mstatus CSR fflags CSR mcause CSR medeleg CSR privilege mode Physical Memory Protection MulDiv module remainder register Branch Target Buffer formal verification symbolic execution model checking ProcessorFuzz paper Sadullah Canakci Chathura Rajapaksha Leila Delshadtehrani Anoop Nataraja Michael Bedford Taylor Manuel Egele Ajay Joshi Boston University University of Washington Architectural Unit instret CSR RTL simulation Hardware Description Language
03
Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL

Processed 22 entities and 26 relations.

22 ent archive
QEMU OpenVADL Vienna Architecture Description Language (VADL) Instruction Set Simulator Dynamic Binary Translation (DBT) Tiny Code Generator (TCG) VADL Intermediate Architecture Model (VIAM) TCG Transformation Decoder Generation Instruction Set Architecture (ISA) RISC-V Cycle-Approximate Simulator C-Code Generation Lowered VIAM trans_addi TCG Translation Function Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL Johannes Zottele Matthias Raschhofer Benedikt Huber Andreas Krall Technische Universität Wien Embench
04
Generating an Efficient Instruction Set Simulator from a Complete Property Suite

Processed 51 entities and 65 relations.

51 ent archive
Instruction Set Simulator Instruction Set Architecture Formal Verification Complete Property Suite Interval Property Checking Bounded Model Checking Interpretive Simulation Compiled Simulation Just-in-Time Compiled Simulation Architectural State Register Transfer Level Architectural Style Properties Completeness Analysis Mapping Function Safety Property Finite State Machine Boolean Satisfiability Pre-Silicon Software Development Pipelined Processor Instruction Decoding Instruction Caching Next State Function Operation Property Design Under Verification Gate-Level Simulation Architecture Description Language ITL LISA OneSpin IPC Verification Tool Generated C++ ISS write_reg macro next_state macro decode macro instrADD property isa property Generating an Efficient Instruction Set Simulator from a Complete Property Suite Ulrich Kühne Sven Beyer Christian Pichler University of Bremen OneSpin Solutions GmbH VHDL Verilog Processor Pipeline Forwarding Logic Invariant Simulation Performance (MIPS) Freeze Variable Temporal Logic Equivalence Proof Program Counter Register File
01
RISC-V source class riscv_asm_program_gen, the brain behind ...

Processed 26 entities and 36 relations.

26 ent archive
riscv-dv CHIPS Alliance RISC-V random instruction generation UVM RTL riscv_asm_program_gen riscv_instr_gen_config riscv_instr_base_test gen_program get_directed_instr_stream add_directed_instr_stream gen_program_header gen_section init_gpr generate_directed_instr_stream insert_sub_program push_gpr_to_kernel_stack riscv_instruction_sequence directed instruction stream general purpose register initialization trap handling interrupt and exception handling RISC-V assembly program generation privilege mode page table
02
[PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

Processed 65 entities and 65 relations.

65 ent archive
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation Nursultan Kabylkas Tommy Thorn Shreesha Srinath Polychronis Xekalakis Jose Renau UC Santa Cruz Esperanto Technologies Intel Nvidia Logic Fuzzer Dromajo co-simulation golden model design-under-test RISC-V random instruction generation Random Instruction Generator reference model comparison end-of-simulation comparison trace comparison formal verification simulation-based verification functional coverage toggle coverage checkpoint congestor table mutator mispredicted path fuzzing branch predictor Branch Target Buffer Reorder Buffer outlier bugs RTL DPI phase analysis input-stimuli fuzzing asynchronous interrupts Debug Transport Module riscv-dv RFUZZ Whisper Chiffre Chisel FIRRTL PyMTL Imperas OVPsim CVA6 BlackParrot BOOM RISC-V ISA tests OpenHW Group ETH Zurich UC Berkeley University of Washington Boston University Western Digital Imperas Software Ltd TLB cache SPEC benchmarks microarchitectural state architectural state Return Address Stack FIFO
01
Randomized Testing of RISC-V CPUs using Direct

Processed 65 entities and 89 relations.

65 ent archive
TestRIG Direct Instruction Injection Tandem Execution Randomized Instruction Generation RVFI-DII RVFI QCVEngine RISCV-DV PyH2P Spike QEMU QuickCheck JasperGold C-Reduce sailcov Genesys-Pro Verification Engine (VEngine) Tandem Verification Model-based Random Testing Test Case Shrinking Directed-Random Test Sequence Generation Symbolic QED Counterexample-Driven Development Architectural Coverage RISC-V Formal Interface Instruction Sequence Generation Execution Trace Comparison Register Reuse Memory Concurrency Testing Regression Testing Constraint Solving for Instruction Generation CHERI Security Extension RISC-V Sail Language Sail RISC-V Model RVBS Ibex Piccolo Flute Toooba RTL Formal Verification Randomized Testing of RISC-V CPUs using Direct Instruction Injection Alexandre Joannou Peter Rugg Jonathan Woodruff Franz A. Fuchs Marno van der Maas Matthew Naylor Michael Roe Robert N. M. Watson Peter G. Neumann Simon W. Moore Claire Wolf Brian Campbell DARPA University of Cambridge Axe Memory Consistency Checker Sequence Import/Export Non-shrinkable Sequences Assertions in Instruction Sequences Pipeline Performance Testing L3 Specification Language riscv-tests Tandem Execution
02
MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

Processed 46 entities and 65 relations.

46 ent archive
MorFuzz Runtime Instruction Morphing Synchronizable Co-simulation Stimulus Template Coverage-Guided Fuzzing Processor Fuzzing Hardware Fuzzing RTL Simulation ISA Simulation RISC-V Instruction Set Architecture Instruction Stream Generation Processor State Coverage Co-simulation State Verification Instruction Field Level Mutation Program Semantic Level Mutation Instruction Shuffle Control Register Coverage State Synchronization Constrained Random Verification Formal Verification DifuzzRTL TheHuzz riscv-dv Spike Synopsys VCS FIRRTL riscv-torture CVA6 Rocket BOOM Morpher Hardware Logic Block Fuzzing Execution Environment Random Number Generator Testing Block Pipeline Hazard Generation Watchpoint Instruction MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation Jinyan Xu Yiyuan Liu Sirui He Haoran Lin Yajin Zhou Cong Wang Zhejiang University City University of Hong Kong UC Berkeley
04
RISC-V Microarchitecture Verification Approaches

Processed 33 entities and 29 relations.

33 ent archive
RISC-V ISA CPU microarchitecture processor verification pipeline speculative execution out-of-order execution Spectre Meltdown constrained-random instruction generation simulation-based verification formal verification hardware-assisted validation virtual prototyping simulation acceleration hardware prototyping reference model comparison coverage-driven verification custom instruction verification UVM SystemVerilog SystemVerilog assertions RTL ALU SoC integration instruction sequence generation RISC-V International ARM x86 test generator security verification custom instruction verification
05
[PDF] Functional Verification of a RISC-V Vector Accelerator - UPCommons

Processed 28 entities and 41 relations.

28 ent archive
RISCV-DV Spike constrained-random test generation co-simulation UVM UVM scoreboard UVM agent virtual sequence SystemVerilog Assertions functional coverage RISC-V Vector extension (RVV) Open Vector Interface (OVI) reference model random RISC-V assembly test generation CI/CD pipeline Jenkins GitLab Vector Processing Unit (VPU) RTL blacklisting instructions unordered floating-point reduction reference model UVM testbench Functional Verification of a RISC-V Vector Accelerator Barcelona Supercomputing Center SemiDynamics European Processor Initiative Google RISC-V ISA
01
Test Program Generation for a Microprocessor: A Case Study

Processed 44 entities and 39 relations.

44 ent archive
Test Program Generation for a Microprocessor: A Case-Study Achim D. Brucker Abderrahmane Feliachi Yakoub Nemouchi Burkhart Wolff SAP AG Univ. Paris-Sud, Laboratoire LRI Common Criteria EAL 7 certification kit model-based test case generation test program generation conformance testing black-box testing white-box testing symbolic test case generation unit testing sequence testing state-exception monad higher-order logic Instruction Set Architecture RISC processor pipelining stuck-at-fault model constraint solving random test generation test oracle formal verification deductive verification theorem proving hardware-in-the-loop testing memory management unit virtual memory VAMP ISA VAMP HOL-TestGen Isabelle/HOL Z3 SMT solver CompCert Verisoft project ASMcoret record is_ASMcore predicate execVAMP function instr datatype CNF normal form
02
Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

Processed 32 entities and 31 relations.

32 ent archive
Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5 Randal E. Bryant Carnegie Mellon University University of California, Berkeley Semiconductor Research Corporation National Science Foundation Microsoft Research UCLID5 Z3 Y86-64 Intel64 x86-64 Formal Verification Pipelining Burch-Dill Correspondence Checking Abstraction Function Satisfiability Modulo Theories Liveness Verification Data Forwarding Branch Prediction Hazard Detection Term-Level Modeling Uninterpreted Functions Symbolic Simulation Pipeline Flushing HCL Control Logic Description Burch Dill O'Hallaron SEQ Sequential Reference Model Arithmetic Logic Unit Register File
03
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

Processed 31 entities and 32 relations.

31 ent archive
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study Vladimir Herdt Daniel Große Eyck Jentzsch Rolf Drechsler DFKI GmbH Johannes Kepler University Linz MINRES Technologies GmbH University of Bremen RISC-V Register-Transfer Level Cross-Level Testing Simulation-Based Verification Instruction Stream Generation Instruction Set Simulator Co-Simulation MINRES TGF RISC-V Core RISC-V Torture Test Model-Based Test Generation Coverage-Guided Fuzzing Formal Methods Control and Status Register Transaction Level Modeling SystemC Co-Simulation Testbench Core Adapter Test Controller Instruction Stream Generator On-the-Fly Instruction Stream Evolution Instruction Fetch Matching RV32I
04
RISC-V Test Generation: Random & Directed for Coverage ...

Processed 38 entities and 32 relations.

38 ent archive
RISC-V ISA Constrained-Random Testing Directed Testing Hybrid Verification Methodology Coverage Closure Functional Coverage Shift-Left Verification Lock-Step Compare Privilege-Mode Transitions Page Table Walk Physical Memory Protection Sv39 Sv48 TLB Flush Logic Self-Checking Tests RTL Stimulus Coverage Cache Coherence Floating-Point NaN STING ImperasDV ImperasFC ImperasSC ImperasTS-ISA ImperasTS-VECT ImperasTS-MMU ImperasTS-PMP ImperasTS-ePMP Verdi VCS ZeBu HAPS Synopsys RVA22 RVA23 Stimulus Graphs Coverage-Driven Verification SystemVerilog Coverage Models
05
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

Processed 30 entities and 34 relations.

30 ent archive
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing Niklas Bruns Vladimir Herdt Daniel Große Rolf Drechsler University of Bremen DFKI GmbH Johannes Kepler University Linz Coverage-Guided Fuzzing Cross-Level Verification RTL Processor Verification Co-Simulation AFL LLVM libFuzzer RISC-V VexRiscv Instruction Set Simulator Mutation-Based Fuzzing Symbolic Execution Model Checking Bayesian Network Test Generation Virtual Coverage Translation Buffer Execution Controller Register Value Comparison Test Vector Post-Processing RV32I Microsoft Google
2026-05-24
arxiv:2511.08443v2
01
Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts

Processed 17 entities and 17 relations.

17 ent archive
Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts Gideon Geier Pariya Hajipour Jan Reineke Hardware-software leakage contracts Side-channel security Coverage-guided hardware-software contract fuzzing Self-compositional framework Microarchitectural state divergence Self-Composition Deviation (SCD) Pre-silicon fuzzing RISC-V Rocket Core BOOM core Spectre Information leakage Hardware fuzzing