Skip to content
STIMSMITH

STIMSMITH

stimulus knowledge
knowledge graph warming up…
explore via search or browse
most connected
riscv-dv
Tool · 262 links
8,858
entities
15,349
relationships
+11 entities · +4 links — latest run (2026-09-30)
activity
02
[PDF] Liste der Publikationen im Scale4Edge Projekt der Universität ... - TIB

Processed 19 entities and 17 relations.

19 ent archive
RISC-V Constrained random verification Coverage-guided fuzzing Symbolic execution Concolic testing Metamorphic testing Mutation-based compliance testing ISA-Level Mutation Classes Unified HW/SW coverage RVX SISL Constrained random verification for RISC-V: overview, evaluation and discussion Processor verification using symbolic execution: A RISC-V case-study Unified hw/sw coverage: A novel metric to boost coverage-guided fuzzing for virtual prototype based hw/sw co-verification Efficient cross-level processor verification using coverage-guided fuzzing Mutation-based compliance testing for RISC-V Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification Metamorphic testing for processor verification: A RISC-V case study at the instruction level RVX-a tool for concolic testing of embedded binaries targeting RISC-V platforms
01
Architecture independent test templates for virtual machines and ...

Processed 12 entities and 18 relations.

12 ent archive
Test Program Test Template Architecture-Independent Test Template Architecture-Dependent Constructs Implementations of Architecture-Dependent Constructs Template Customization for Target Architecture Implementation Selection Strategy Brute-Force Selection Random Selection Third-Party Generators Interface for Architecture-Dependent Constructs Architecture-Independent Template Generation Method
03
Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

Processed 9 entities and 4 relations.

9 ent archive
Google RISCV-DV Imperas RISC-V Processor Verification IP (VIP) Imperas Floating-Point Architectural Validation Test Suites Imperas Instruction Stream Test Generator RV32F Floating-Point Architectural Validation Test Suite RV64F Floating-Point Architectural Validation Test Suite RV64D Floating-Point Architectural Validation Test Suite RV32/64IMC Test Suites RISC-V Vector Test Suite
01
[PDF] RISC-V Processor Verification with Coverage-guided Aging*

Processed 12 entities and 19 relations.

12 ent archive
RISC-V DV riscv-torture RISC-V instruction stream generator Coverage-guided aging Coverage-guided fuzzing Symbolic execution Constraint-based specification Endless randomized instruction stream generation Randomized test strategy RISC-V Processor Verification with Coverage-guided Aging Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging Mutation-based compliance testing for RISC-V
04
FLAME: Enhancing Functional Coverage in

Processed 31 entities and 35 relations.

31 ent archive
FLAME Constrained Random Verification (CRV) Coverage-Guided Fuzzing (CGF) RISCV-DV Cascade LLM-PVISA LLM-PVFunc ChatFuzz VerilogReader LLM4DV MorFuzz DifuzzRTL Retrieval-Augmented Generation (RAG) Chain-of-Thought (CoT) Zero-shot prompting Few-shot learning Documents–Instructions–Programs CoT Instruction Set Simulator (ISS) RISC-V GCC Synopsys VCS C test programs RISC-V instruction sequences GPT-3.5-Turbo CodeLlama-7B-Instruct CodeLlama-13B-Instruct Phind-CodeLlama-34B-v2 ChatGPT Llama 3 RISC-V Directed testing Random testing
05
ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT

Processed 23 entities and 32 relations.

23 ent archive
ConfigDrivenV Python UVM SystemVerilog Constrained random test generation Directed testing Python-UVM co-verification Golden reference model Random instruction generation File I/O bridge (Python to UVM) $fscanf instr.hex checkpoints.mem golden.mem UVM sequence cpu_test.sv RISC-V Power ISA SystemVerilog constraint randomization UVM Verification of RISC-V Instruction Set (ICAECA 2024) A UVM based Reusable Framework for End-To-End Verification of Power ISA Cores (IJISAE 2024) Directed Test Generation for Hardware Validation: A Survey (ACM CS 2023) Automated Testing, Verification and Repair of RTL Hardware Designs (UCB EECS TR 2024-157)
01
PySpike: Agile Co-Verification of RISC-V SoC's and Beyond

Processed 31 entities and 35 relations.

31 ent archive
PySpike Spike RISC-V ISA co-verification differential testing SoC RTL Python in Spike (PIS) Spike in Python (SIP) MMIO device model custom instruction extension RISC-V disassembler OpenOCD test program CPU trace log dlopen plugin system ISA string parser spike PyPI package riscv.sim Python module riscv.isa_parser Python module agile co-verification methodology executable specification LIU Yu EsionTech HuiMt Labs UC Berkeley riscv-dv Towards Developing High Performance RISC-V Processors Using Agile Methodology Python bindings pytest GitHub Actions
2026-09-16
usenix.org/system
01
[PDF] Cascade: CPU Fuzzing via Intricate Program Generation - USENIX

Processed 52 entities and 79 relations.

52 ent archive
Cascade asymmetric ISA pre-simulation CPU fuzzing differential fuzzing program reduction coverage-guided fuzzing intermediate program construction control flow entanglement with data flow bug detection via program non-termination offset construction progressive memory allocation formal verification RTL simulation multiplexer select coverage control register coverage mutation-based test-case generation golden model comparison DifuzzRTL TheHuzz RFUZZ Spike Verilator Yosys HypFuzz RISC-V ISA Instruction Set Simulator (ISS) basic block cf-ambiguous instruction Control and Status Registers (CSRs) RTL design program completion rate prevalence of fuzzing instructions dependency chain privilege transition Floating-Point Unit (FPU) self-modifying code correct-by-construction programs fuzzing throughput register lifecycle state machine Cascade: CPU Fuzzing via Intricate Program Generation Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich USENIX VexRiscv PicoRV32 Kronos CVA6 Rocket core BOOM Cascade source code
2026-09-15
cse.cuhk.edu.hk/~byu
01
[PDF] Learning to Update Test Sequences for Coverage-Guided Verification

Processed 60 entities and 66 relations.

60 ent archive
DeepVerifier Coverage-Guided Verification Test Sequence Generation RISC-V ISA Simulation-Based Verification Functional Verification RTL Simulation Coverage Score Prediction Constrained Random Generation Coverage-Guided Fuzzing Gradient-Based Sequence Optimization Instruction Sequence Representation Transformer Language Model BART LSTM Multi-Head Self-Attention Sinusoidal Positional Encoding Cross-Entropy Loss Mean Square Error Loss AdamW Optimizer Mutational Fuzzing Concolic Testing Static Formal Analysis Bayesian Network GELU Activation Token Embedding FORCE-RISCV Synopsys VCS Verilator BOOM RocketChip PyTorch Hugging Face Transformers PalmTree BERT GPT RoBERTa Random Instruction Generator RISC-V Instruction Syntax Interpreter Custom RISC-V Tokenizer Coverage Score Predictor MLP Coverage Metrics Line Coverage Toggle Coverage Branch Coverage Sequential Modeling Task ELF File Control Flow Graph Yuntao Lu Chen Bai Yuxuan Zhao Ziyue Zheng Yangdi Lyu Mingyu Liu Bei Yu The Chinese University of Hong Kong The Hong Kong University of Science and Technology Huawei Technologies DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification Concolic Testing
01
RISC-V Verification IP: Scope, Limits and CPU Sign-Off

Processed 33 entities and 40 relations.

33 ent archive
RISC-V Verification IP Instruction-Stream Generator riscv-dv RISC-V Verification Interface (RVVI) UVM Environment Reference Model Instruction-Set Simulator (ISS) Functional Coverage RTL RISC-V ISA CPU Directed Test Constrained-Random Stimulus Generation Retirement-Level Checking Co-simulation Architectural Certification Tests (ACT) Formal Verification Software-Driven CPU/SoC Test Verification Plan RVVI-API RVVI-TRACE CHIPS Alliance OpenHW Group CORE-V-VERIF Accellera Systems Initiative riscv-formal YosysHQ Custom RISC-V Instruction Verification SoC Integration Verification Code Coverage Protocol VIP Assertions and Checkers Emulation and FPGA Prototyping
01
ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits

Processed 64 entities and 67 relations.

64 ent archive
ReFuzz Processor Fuzzing Contextual Bandit Differential Testing Mutation-Based Fuzzing Direct Testing Random Testing Test Minimization Coverage-Guided Fuzzing Seed Generation Integer Programming Epsilon-Greedy Exploration TheHuzz Cascade American Fuzzy Lop Synopsys VCS Spike Chipyard MABWiser MINTS Prior-Processor Tests Processor-Under-Test Golden-Reference Model Branch Coverage Incremental Coverage Coverage Context Vulnerability Test Coverage Matrix Instruction Set Architecture Design Reuse Pre-Silicon Verification Denial-of-Service Attack Memory Deadlock Reorder Buffer Control and Status Register minstret Register Speculative Execution Vulnerability FENCE.I Instruction Page Table Entry Exploration-Exploitation Tradeoff Instruction Sequence Common Weakness Enumeration RTL Finite-State Machine Out-of-Order Execution ReFuzz: Reusing Tests for Processor Fuzzing with Contextual Bandits Chen Chen Zaiyan Xu Mohamadreza Rostami David Liu Dileep Kalathil Ahmad-Reza Sadeghi Jeyavijayan Rajendran Texas A&M University Technische Universitat Darmstadt RISC-V CVA6 Rocket Core BOOMV3 BOOMV4 RSD Processor PicoRV32 Chisel FDIV Bug
02
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection

Processed 30 entities and 30 relations.

30 ent archive
Specure BOOM Chipyard SpecDoctor TheHuzz RISC-V speculative execution hardware fuzzing differential fuzzing Leakage Path information flow tracking microarchitectural snapshot (M)WAIT vulnerability Zenbleed Spectre code coverage Potential Direct Leakage Channel golden-reference model CWE-1342 register rename stage maptable rollback CSR register out-of-order processor pre-silicon fuzzing umonitor instruction umwait instruction Ormandy Intel Xeon processor static information flow tracking RTL
2026-09-07
cs.rice.edu/~vardi
01
On Parallel Scalable Uniform SAT Witness Generation

Processed 50 entities and 68 relations.

50 ent archive
Constrained-Random Verification Uniform Stimulus Generation SAT Witness Sampling Almost-Uniform Sampling Random Hashing Universal Hashing XOR Hash Functions Conjunctive Normal Form Approximate Model Counting Functional Verification Design Under Verification Parallel Stimulus Generation Interval Propagation Markov Chain Monte Carlo Sampling Random Seeding of SAT Solver Weighted Binary Decision Diagram Independent Support Bounded Model Checking Leapfrogging Optimization UniGen2 UniGen UniWit ApproxMC BSAT Enumeration Belief Network Constraint Conversion CryptoMiniSAT RACE On Parallel Scalable Uniform SAT Witness Generation Supratik Chakraborty Daniel J. Fremont Kuldeep S. Meel Sanjit A. Seshia Moshe Y. Vardi Armando Solar-Lezama Mate Soos Mark Jerrum Leslie Valiant Vijay Vazirani Indian Institute of Technology Bombay University of California Berkeley Rice University Intel EstimateParameters Algorithm GenerateSamples Algorithm Parallel UniGen2 ISCAS89 Benchmark Circuits SMTLib Benchmarks r-wise Independent Hash Functions Dennard Scaling Belief Network Constraint Conversion
01
From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV

Processed 42 entities and 51 relations.

42 ent archive
RVVTS Automated Failure Categorization RISC-V Vector Extension Ara vector processor coverage-guided test generation single-instruction isolation positive testing negative testing RISC-V Vector Tests Generator RISCV-DV FORCE-RISCV Spike Verilator RTL verification functional coverage grammar-based test generation code minimization Machine State AraRunner Ara test harness CVA6 ELF binary SIMD constraint solving Universal Verification Methodology co-simulation riscvOVPsim Sail-RISC-V CHIPS Alliance Johannes Kepler University Linz DFKI Bremen Manfred Schlägl Jonas Reichhardt Daniel Grosse Valid Sequences test set Invalid+Valid Sequences test set failure mode category symbolic execution RISC-V Torture Test Generator RISC-V VP++ QEMU From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
02
Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking

Processed 51 entities and 72 relations.

51 ent archive
Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking Shoham Shitrit Sreepathi Pai University of Rochester GPU instruction set formal semantics mutation testing equivalence checking test suite generation model-based test generation bounded model checking stratified random sampling executable semantics PTX instruction set NVIDIA CBMC MUSIC SAIL K framework libFuzzer KLEE SeaHorn LLBMC MiniSAT CVC4 CVC3 mutation score counterexample generation floating-point arithmetic IEEE floating point semantics undefined behaviour non-determinism differential testing coverage-guided fuzzing dynamic symbolic execution litmus tests instruction set simulator SMT-LIB SAT/SMT solvers add.rm.ftz.sat.f32 C semantics test suite generation pipeline path coverage ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS A Complete Formal Semantics of x86-64 User-level Instruction Set Architecture ISA formal semantics x86 instruction set RISC-V ARMv8 instruction set subnormal floating point numbers differential symbolic execution LLVM
2026-09-03
arxiv:2601.07593v1
01
GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation

Processed 57 entities and 66 relations.

57 ent archive
RTL verification stimuli generation test plan generation two-stage test plan generation framework testbench generation constrained random generation supervised fine-tuning Group Relative Policy Optimization GRPO with State Mutation tree-based branching mutation strategy mutation testing reinforcement learning for language models reward modeling random test generation functional equivalence checking retrieval-augmented generation iterative refinement multi-agent framework coverage-driven verification RTL design verification golden RTL pass rate mutation detection rate input stimuli sub-unit RTL verification reward sparsity advantage computation sequential circuit verification combinational circuit verification data contamination DeepSeek-R1 Claude-4.0-Sonnet DeepSeek-R1-distill-Qwen-7B LLaMA-3.1-405B Claude3.7-Sonnet ScaleRTL-32B DAPO GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation ScaleRTL: scaling LLMs with reasoning data and test-time compute for accurate RTL code generation VerilogEval: evaluating large language models for Verilog code generation BugGen: a self-correcting multi-agent LLM pipeline for realistic RTL bug synthesis VeriDebug Comprehensive Verilog Design Problems (CVDP) benchmark DeepSeekMath: pushing the limits of mathematical reasoning in open language models VeriContaminated: assessing LLM-driven Verilog coding for data contamination RTLLM: an open-source benchmark for design RTL generation with large language model DAPO: an open-source LLM reinforcement learning system at scale Decomposed prompting: a modular approach for solving complex tasks Dimple Vijay Kochar Nathaniel Pinckney Haoxing Ren Brucek Khailany Chenhui Deng MIT NVIDIA Research ScaleRTL dataset SFT training dataset GRPO-SMu training dataset testbench template
01
[PDF] GenHuzz: An Efficient Generative Hardware Fuzzer - USENIX

Processed 51 entities and 68 relations.

51 ent archive
GenHuzz Hardware-Guided Reinforcement Learning hardware fuzzing whitebox fuzzing differential testing Proximal Policy Optimization reinforcement learning coverage-based fuzzing RISC-V assembly instruction generation RISC-V ISA test case generation hardware coverage feedback intra-instruction semantics inter-instruction semantics reward function fuzzing policy mutation-based instruction generation Golden Reference Model RTL simulation Device Under Test word-level tokenization reset module for exploration-exploitation balance Physical Memory Protection Load-Reserved/Store-Conditional instructions cross-entropy loss minimization mismatch detection DifuzzRTL TheHuzz ChatFuzz Cascade Spike RISC-V ISA simulator RocketChip Boom CVA6 GPT-2 GPT-based language model fuzzer transformer architecture FSM coverage condition coverage line coverage Lichao Wu Mohamadreza Rostami Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi Technical University of Darmstadt Texas A&M University RISC-V 32/64-bit ISA training dataset instruction tokenization and encoding execution trace comparison coverage-based fuzzing
02
[PDF] RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential ...

Processed 59 entities and 71 relations.

59 ent archive
RISCVuzz Differential CPU Fuzzing Instruction Sequence Generation Bottom-Up Instruction Space Exploration Encoding-Based Instruction Filtering Majority Vote Differential Analysis Static Binary Compilation for Noise Removal Sandbox State Protection Lazy Page Mapping Alarm-Based Infinite Loop Prevention Post-Silicon Fuzzing RTL Fuzzing RISC-V ISA Architectural CPU Vulnerability Halt-and-Catch-Fire CPU Vulnerability GhostWrite RISC-V Vector Extension XTheadMemIdx Extension Instruction Space Coverage Non-Determinism in Instruction Effects Differential Fuzzing Physical Memory Write Primitive Virtual Memory Bypass Transient-Execution Attack MMIO Privilege Levels in RISC-V Paging and Virtual Memory Reproducer File Instruction Encoding Space CSR Instructions QEMU Cascade DifuzzRTL RISC-V Opcodes Repository Nix Build System rvv-bench RISCVuzz Client (C and RISC-V Assembly) RISCVuzz Server Runner Sandbox RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing Fabian Thomas Lorenz Hetterich Ruiyi Zhang Daniel Weber Lukas Gerlach Michael Schwarz CISPA Helmholtz Center for Information Security T-Head SiFive Scaleway T-Head XuanTie C906 CPU T-Head XuanTie C908 CPU T-Head XuanTie C910 CPU SiFive U54 CPU SiFive U74 CPU vse128.v Instruction Fuzzing Throughput Optimization Multi-Core Fuzzing Parallelization Sequence Length Scaling
01
Verify RISC-V Custom Instructions: From Spec to Sign-Off

Processed 38 entities and 51 relations.

38 ent archive
RISC-V custom RISC-V instruction RTL ISA custom-instruction verification contract reference model constrained-random stimulus generation directed semantic tests functional coverage retirement-level lockstep co-simulation architectural state comparison at instruction retirement formal verification instruction-stream generation UVM CPU riscv-dv Spike Sail RISC-V Architectural Certification Tests ACT4 framework custom opcode space (custom-0 through custom-3) operand space partitioning register aliasing privilege mode verification decoder overlap checking software toolchain enablement CHIPS Alliance RISC-V International Alpinum Consulting XLEN CSR regression testing coverage closure instruction encoding exception and trap behaviour pipeline hazard verification data dependency stimulus vendor extension naming convention
02
Coverage Plan — Ibex Documentation 0.1.dev50+geede2fbbe documentation

Processed 41 entities and 36 relations.

41 ent archive
Instruction Category ALU Instruction Category Mul Instruction Category Div Instruction Category Branch Instruction Category Jump Instruction Category Load Instruction Category Store Instruction Category CSRAccess Instruction Category EBreakDbg Instruction Category EBreakExc Instruction Category ECall Instruction Category MRet Instruction Category DRet Instruction Category WFI Instruction Category Fence Instruction Category FenceI Instruction Category FetchError Instruction Category CompressedIllegal Instruction Category UncompressedIllegal Instruction Category CSRIllegal Instruction Category PrivIllegal Instruction Category OtherIllegal Instruction Category None Instruction Category Compressed Instruction Uncompressed Instruction Instruction Fetch Stage Instruction Decode Execute Stage Decompression RV32M Extension Zicsr Extension RISC-V ALU Illegal Instruction Exception Debug Mode Privilege Level M-mode ibex_pkg::OPCODE_OP ibex_pkg::OPCODE_OP_IMM dcsr.ebreakm dcsr.ebreaku
01
RISC-V Verification: A Guide to Co-Simulation

Processed 33 entities and 46 relations.

33 ent archive
Lockstep Co-Simulation Retirement-Level Lockstep Architectural State Instruction Retirement Asynchronous Events Step-and-Compare Methodology Constrained-Random Instruction Streams Directed ISA Tests Configurable State Mask Weak Memory Model Virtual Memory Operations CSR Side Effects RTL Reference Model Co-Simulation Harness Checkpoint and Seed Logging Randomised Interrupt Injection Mismatch Reporting RVVI RISC-V UVM ImperasDV ImperasFPM VCS Verdi Synopsys Imperas S. Davidmann A. Sutton L. Moore Understanding the RISC-V Verification Ecosystem RISC-V Processor Verification Requires the Full Toolbox SystemVerilog
2026-08-25
d-nb.info/1255631414
01
Advanced virtual prototyping for cyber-physical systems ...

Processed 65 entities and 76 relations.

65 ent archive
Vladimir Herdt Rolf Drechsler University of Bremen DFKI GmbH RISC-V Virtual Prototype (VP) SystemC TLM Instruction Set Architecture (ISA) RISC-V VP QEMU SPIKE RV8 gem5 Renode FORVIS GRIFT SAIL-RISCV ETISS Dynamic Binary Translation (DBT) Universal Verification Methodology (UVM) RISCV-DV Constrained-Random Test Generation Fuzzing-based Test Generation Compliance Testing RTL Verification Instruction Set Simulator (ISS) Instruction Stream Generator (ISG) Concolic Testing Symbolic Execution Coverage-Guided Fuzzing (CGF) Dynamic Information Flow Tracking (DIFT) RISC-V Torture Test Generator Formal Verification Stateful Symbolic Simulation Partial Order Reduction (POR) State Subsumption Reduction (SSR) Cross-Level Co-Simulation Intermediate Verification Language (IVL) KLEE SAGE S2E Angr libFuzzer AFL RVX Cyber-Physical Systems (CPS) Internet-of-Things (IoT) Mutation Testing Signature-Based Test Infrastructure High-Level Synthesis (HLS) Design Space Exploration GDB Remote Serial Protocol (RSP) Eclipse IDE Timing Model Just-in-Time Compilation (JIT) Control and Status Registers (CSRs) RISC-V Privileged Architecture Embedded Software Verification SiFive HiFive1 Board Linux Operating System FreeRTOS Zephyr RTOS RIOT OS Advanced Virtual Prototyping for Cyber-Physical Systems Using RISC-V
2026-08-23
llm.ics.jku.at/files
01
FP-RVVTS: Sail-guided Verification of

Processed 40 entities and 54 relations.

40 ent archive
FP-RVVTS Sail RISC-V RISC-V Floating-Point (FP) Instruction Verification Grammar-Based FP Instruction Sequence Generation Differential Execution Dependency-Based Test-Case Minimization Automated Failure Characterization Positive and Negative Test Generation Failure Isolation Functional Coverage Measurement NaN-Boxing RTL Design Verification Spike RISC-V VP++ QEMU SoftFloat FloppyFloat riscvOVPSim PULP ARA RISCV-DV Cascade Instruction Set Simulator (ISS) FP Exception Flag Generation Rounding Mode IEEE 754 Floating-Point Standard Cross-Level Testing Mutation-Based Compliance Testing UVM-Based Verification Environment Machine State Comparison FP Grammar Production Rules SailRunner ExecutionRunner Katharina Ruep Manfred Schlägl Daniel Große Johannes Kepler University Linz RISC-V International Dependency Annotations Test-Set Generation Sub-Flow Test-Set Execution Sub-Flow
02
GoldenFuzz: Generative Golden Reference Hardware Fuzzing - University of Bristol

Processed 22 entities and 21 relations.

22 ent archive
GoldenFuzz hardware fuzzing Golden Reference Model Device Under Test ISA compliance instruction block construction coverage-guided feedback test case refinement two-stage fuzzing framework digital twin RocketChip BOOM CVA6 BA51-H RISC-V GoldenFuzz: A Novel Two-Stage Hardware Fuzzing Framework Lichao Wu Mohamadreza Rostami Huimin Li Nikhilesh Singh Ahmad-Reza Sadeghi Internet Society
01
HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing | alphaXiv

Processed 54 entities and 51 relations.

54 ent archive
HiFuzz DifuzzRTL Cascade Hardware Fuzzing Constrained-Random Verification Mutation-Based Fuzzing Constructive Fuzzing Hierarchical Reinforcement Learning Reinforcement Learning Proximal Policy Optimization Semantic-Aware Basic Block Encoding Adaptive Coverage Reward Mechanism Upper Confidence Bound Multi-Armed Bandit Bidirectional LSTM Sparse Reward Problem Intrinsic Reward Coverage Masking Effect Design Under Test Golden Reference Model Program Agent Basic Block Agent Test Program Generation Instruction Set Architecture RISC-V Structured Tokenizer Dependency Chain Instruction Prevalence Hardware Coverage Formal Verification Out-of-Order Execution Rocket Core BOOM Core CVA6 Cascade: CPU Fuzzing via Intricate Program Generation DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs Proximal Policy Optimization Algorithms Between MDPs and Semi-MDPs: A Framework for Temporal Abstraction in Reinforcement Learning Finite-Time Analysis of the Multiarmed Bandit Problem F. Solt K. Ceesay-Seitz K. Razavi J. Schulman F. Wolski P. Dhariwal A. Radford O. Klimov R. S. Sutton D. Precup S. Singh P. Auer N. Cesa-Bianchi P. Fischer USENIX Security Symposium
02
[PDF] RISC Whisk: Unleashing the Power of Software Fuzzing on Hardware

Processed 44 entities and 78 relations.

44 ent archive
RISC Whisk Nandita Singh Matthew Hicks Angelos Stavrou Wenjie Xiong hardware fuzzing software fuzzing sparse memory matrix custom mutator input seed random instruction generator constraint block direct programming interface executable binary line coverage coverage-based verification functional verification formal verification emulation-based verification assertion-based verification FPGA-based verification RTL mutation tree instruction set architecture memory modeling wishbone interface black-box fuzzing white-box fuzzing feedback-based fuzzing Program Under Test AFL++ Verilator Picorv Sodor1 Sodor3 Sodor5 Mor1kx RISC-V OpenRISC 1000 architecture hardware-to-software translation Virginia Polytechnic Institute and State University RISC-V Foundation testbench design verification
02
An SPU Reference Model for Simulation, Random Test Generation and Verification

Processed 36 entities and 40 relations.

36 ent archive
Synergistic Processing Unit (SPU) Cell Processor Instruction Set Architecture (ISA) SPU Reference Model Random Test Case Generation Genesys Pro (GPro) Instruction Simulator Pipeline Simulator Verification Environment RTL Simulation Floating-Point Model IEEE 754 Floating-Point Standard Function Coverage DMA Transaction Self-Modifying Code ECC Error Handling Check-pointing Streaming I/O APUOP Common Definition File Mambo Full System Simulator COFF Format Assembler In-Order Processor Yukio Watanabe Balazs Sallay Brad Michael Daniel Brokenshire Hazim Shafi Daisuke Hiraoka Toshiba Corporation IBM Sony Computer Entertainment Inc. An SPU Reference Model for Simulation, Random Test Generation and Verification INTERPRETER_exec() APU_t struct Channel Access Transaction
03
End-to-End Verification of ARM Processors with ISA-Formal

Processed 40 entities and 53 relations.

40 ent archive
ISA-Formal ARM Limited Bounded Model Checking Formal Verification Simulation-Based Verification Instruction Set Architecture (ISA) Pipeline Forwarding Out-of-Order Execution Register Renaming Reorder Buffer Instruction Fusion Dual Issue Pipeline Abstraction Function Pipeline Follower End-to-End Verification Burch-Dill Flushing Refinement Completion Refinement Architecture Explorer Architecture Specification Language (ASL) ARM Architecture Reference Manual RTL (Register Transfer Level) SystemVerilog Subset Behaviour Checking Abstract Functions (Oracle-based Verification) Interface Properties Hand-Written Properties Instruction Sequence (Stimulus) Superscalar Processor Microcontroller (3-stage pipeline) Floating Point Unit (FPU) Monomorphization (Compiler Technique) Constant Propagation Alastair Reid End-to-End Verification of ARM Processors with ISA-Formal ARMv8-A Architecture ARMv8-M Architecture Unconstrained Opcode (Free Stimulus) Assumption-Based Bug Workaround Instruction Class Enumeration Micro-op (micro-operation)
01
LLM-based Processor Verification: A Case Study for ...

Processed 44 entities and 62 relations.

44 ent archive
LLM-based Processor Verification: A Case Study for Neuromorphic Processor simulation-based verification random test generation constrained random generation coverage-directed test generation coverage-directed test selection LLM-based test generation RAVEN RISCV-DV GPT-3.5 GPT-4 large language model domain specific architecture neuromorphic processor neuromorphic instruction set RISC-V Xuantie-C910 RTL simulation code coverage block coverage expression coverage toggle coverage ISA coverage prompt engineering hardware-aware test generation assembly test generation C program test generation novelty-driven verification Codex DAVE Chip-Chat ChipGPT design under test iterative test refinement functional verification branch prediction TrueNorth ISA extension method National University of Defense Technology University of Electronic Science and Technology of China Defense Innovation Institute Chao Xiao Lei Wang LLM-based verification workflow
01
Specification-Driven Testbench Development for

Processed 33 entities and 39 relations.

33 ent archive
stimulus generator testbench test sequence generation cycle-accurate formal specification control flow graph Hoare triple generalized FSM model FSM traversal multistimulus execution channel microoperation stage driver stage monitor mediator response checker coverage tracker parallel-pipeline design semi-formal verification functional coverage interlock coverage multistimulus coverage precondition postcondition RTL model CTESK SeC Institute for System Programming of the Russian Academy of Sciences Mikhail Chupilko Alexander Kamkin MIPS64-compatible microprocessor L2 cache model checking simulation-based verification
02
Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging

Processed 76 entities and 98 relations.

76 ent archive
Prelude Priming-Guided State Reconstruction Snapshot-Based Debugging Visibility Warm-Up Differential Testing Cycle-Accurate Replay Memory Footprint Analysis Scan-Chain-Based State Capture State Readback RTL Simulation FPGA-Based Prototyping Full-State Capture Micro-Architectural State Reconstruction Signal Tracing DESSERT ENCORE StateMover STATE-ACCESS VCS Verilator ILA SignalTap ChipScope Spike Xilinx Vivado BOOM Rocket RISC-V Out-of-Order Execution Architectural Registers Micro-Architectural State Pipeline Reorder Buffer (ROB) Branch Predictor Load-Store Queue (LSQ) Cache Hierarchy ISA Simulator RTL Signal Visibility Physical Register File DPI-C Interface PCIe Interface Data Extract Unit (DEU) Architectural Register Management Unit (AMU) Memory Rebuild Unit (MRU) AMD Virtex UltraScale+ VU19P FPGA CoreMark Embench Memory Footprint Instruction Set Architecture (ISA) Jialin Sun Yuchen Hu Dean You Zhe Jiang Xinwei Fang Southeast University University of York National Center of Technology Innovation for EDA Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging RISC-V DV ProcessorFuzz HyPFuzz Processor Fuzzing Instruction Fetch Unit (IFU) Program Counter (PC) General Purpose Registers (GPRs) Floating Point Registers (FPRs) Control and Status Registers (CSRs) UVLLM ISAAC MEIC RISCVuzz DiffTest-H Superscalar Processor Waveform Tracing Reproduction Rate
04
Specification-Based Test Program Generation for MIPS64 Memory Management Units

Processed 41 entities and 67 relations.

41 ent archive
Specification-Based Test Program Generation for MIPS64 Memory Management Units A.S. Kamkin A.M. Kotsynyak Institute for System Programming of the Russian Academy of Sciences MicroTESK test program generation memory management unit MIPS64 MMUSL Genesys-Pro DeepTrans address translation translation lookaside buffer cache memory symbolic execution constraint solving formal specification test template instruction set architecture nML directed acyclic graph execution path combinatorial test generation page table Ruby Z3 SMT solver CVC4 SMT solver Fortress library MA2TG random test generation domain-specific language instruction set simulator memory segment microprocessor verification test data generation IBM D. Vorobyev A. Tatarnikov buffer-event factorization preparator MicroTESK
01
Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs

Processed 51 entities and 64 relations.

51 ent archive
Constrained Random Verification Cross-Level Verification Mutation Testing Mutation Coverage Functional Coverage RTL Code Coverage Instruction Sequence Length Mutation Location Mutation Count Virtual Prototype Register-Transfer Level RISC-V Instruction Set Architecture Fuzzing Symbolic Execution Formal Verification Input Stimuli Generation Coverage-Guided Feedback SMT Solver Transaction Level Modeling Device Under Verification CRV Strategy Execution Trace Comparison Value Coverage Immediate Value Coverage Register File Access Coverage Saturation Feedback-Based Verification riscv-dv MicroRV32 Yosys RISC-V VP FORCE-RISCV RISC-V Torture Test RTL Mutation Engine Commercial RTL Simulator Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs Sallar Ahmadi-Pour Luca Müller Rolf Drechsler University of Bremen DFKI GmbH CHIPS Alliance ALU Control Unit Fetch Unit Instruction Decoder Multiply-Divide Unit System-on-Chip Binary-Compatible Executable Mutation Generation Scripts RTL Mutation Engine
01
An introduction to RISC-V processor verification techniques

Processed 47 entities and 59 relations.

47 ent archive
RISC-V Design Verification Post-simulation Trace File Compare Self-checking Tests Signature Comparison Step-and-Compare Step-and-Compare with Asynchronous Events Constrained Random Verification Functional Coverage Assertions Verification Planning Instruction Stream Generator Instruction Set Simulator Processor Reference Model RVVI RVVI-TRACE RVVI-API UVM RTL Simulation Co-simulation Verification IP Compliance Tests Asynchronous Events Metric-driven Verification Hybrid Verification Methodology riscvOVPsimPlus ImperasDV riscv-dv Valtrix STING spike riscvISACOV Imperas RVFCgen GCC LLVM Imperas Software RISC-V International OpenHW Group CHIPS Alliance EM Micro SiLabs Lee Moore Aimee Sutton core-v-verif RVVI GitHub Repository CV32E40X RISC-V ISA Extensions SystemVerilog DPI