Program Counter (PC)

Concept

In the provided processor-verification evidence, the Program Counter (PC) is the value used by the instruction memory interface to handle instruction fetching. In a cross-level RTL/ISS co-simulation, each generated instruction is queued together with its PC so the ISS can later match the corresponding RTL-fetched instruction, although PC-only matching can fail when prefetching and jumps reorder fetch and execution timing.

First seen 5/26/2026

Last seen 5/29/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

The Program Counter (PC) appears in the evidence as the value on which instruction fetching is based. In the described cross-level processor-verification testbench, the instruction memory interface handles instruction fetching based on the PC, and both the RTL core and the ISS interact with the instruction stream through fetch operations parameterized by the PC. [C1]

Role in cross-level instruction fetching

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CITATIONS

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7 citations — click to expand

[1] The instruction memory interface handles instruction fetching based on the Program Counter.

[2] An RTL-core instruction fetch generates a new instruction on the fly, even if the PC has already been fetched, while an ISS fetch receives the corresponding RTL-fetched instruction.

[3] The RTL-side instruction-stream function takes a PC, generates an instruction, stores the pair `(PC, instruction)` in a pending queue, and returns the instruction.

[4] The ISS-side matching algorithm searches pending `(PC, instruction)` entries and returns an instruction only when both the queued PC and instruction match the ISS PC and expected instruction.

[5] Feeding the same instruction stream into the RTL core and ISS requires special handling performed by the instruction stream between the instruction generator and memory interfaces.

[6] Direct matching based only on the PC can fail because RTL prefetching around jumps can generate instructions before the ISS has executed the corresponding jump.

[7] Pipeline flushes, stalls, delays, and gaps complicate instruction-completion detection and stream alignment.