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STIMSMITH

MicroRV32

Tool
First seen 6/19/2026
Last seen 8/15/2026
Evidence 16 chunks

NEIGHBORHOOD

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RELATIONSHIPS

16 connections
RISC-V implements → 100% 4e
MicroRV32 is an open source RISC-V based processor implementation.
Processor Verification using Symbolic Execution: A RISC-V Case-Study ← evaluates 100% 4e
The paper presents results on verifying the MicroRV32 processor as a case study.
RISC-V Instruction Set Architecture implements → 100% 2e
MicroRV32 is a RISC-V RTL implementation conforming to the RISC-V ISA.
riscv-formal evaluates → 85% 1e
MicroRV32 was also verified using the riscv-formal tool.
constrained-random instruction generation evaluates → 85% 1e
MicroRV32 was previously tested using constrained random instruction generation techniques.
RV32I Instruction Set implements → 95% 1e
MicroRV32 implements the RV32I instruction set.
SpinalHDL derived from → 90% 1e
MicroRV32 is based on SpinalHDL hardware description language.
Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs ← uses 100% 1e
The paper uses MicroRV32 as the RISC-V RTL SoC implementation under verification.
SpinalHDL part of → 90% 1e
MicroRV32 is a popular open source processor implementation based on SpinalHDL.
Register-Transfer Level implements → 100% 1e
MicroRV32 is an RTL implementation of a RISC-V SoC.
ALU ← part of 100% 1e
MicroRV32 contains an ALU as one of its submodules.
Control Unit ← part of 100% 1e
MicroRV32 contains a Control Unit as one of its submodules.
Fetch Unit ← part of 100% 1e
MicroRV32 contains a Fetch Unit as one of its submodules.
Instruction Decoder ← part of 100% 1e
MicroRV32 contains an Instruction Decoder as one of its submodules.
Multiply-Divide Unit ← part of 100% 1e
MicroRV32 contains a Multiply-Divide Unit as one of its submodules.
System On Chip part of → 100% 1e
MicroRV32 is a RISC-V based System-on-Chip implementation.