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STIMSMITH

MicroRV32

Tool
First seen 6/19/2026
Last seen 7/12/2026
Evidence 13 chunks

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RELATIONSHIPS

7 connections
Processor Verification using Symbolic Execution: A RISC-V Case-Study ← evaluates 100% 4e
The paper presents results on verifying the MicroRV32 processor as a case study.
RISC-V implements → 100% 4e
MicroRV32 is an open source RISC-V based processor implementation.
constrained-random instruction generation evaluates → 85% 1e
MicroRV32 was previously tested using constrained random instruction generation techniques.
RV32I Instruction Set implements → 95% 1e
MicroRV32 implements the RV32I instruction set.
SpinalHDL derived from → 90% 1e
MicroRV32 is based on SpinalHDL hardware description language.
riscv-formal evaluates → 85% 1e
MicroRV32 was also verified using the riscv-formal tool.
SpinalHDL part of → 90% 1e
MicroRV32 is a popular open source processor implementation based on SpinalHDL.