Register-Transfer Level
ConceptRegister-Transfer Level (RTL) is the abstraction at which digital hardware designs are described in terms of data movement between registers and the logical/arithmetic operations performed on that data. RTL designs are written in hardware description languages (HDLs) such as Verilog, VHDL, Chisel, or SystemVerilog, and are used as inputs to hardware simulation, formal verification, hardware fuzzing, logic synthesis, logic locking, and test-generation flows.
First seen 5/25/2026
Last seen 7/18/2026
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Overview
Register-Transfer Level (RTL) is the abstraction at which digital hardware designs are described in terms of the movement of data between registers and the logical/arithmetic operations applied to that data. Hardware designs are not directly executable on a host machine, so they are implemented at RTL and evaluated using an RTL simulator or formal engine. RTL designs are usually expressed in a hardware description language (HDL) such as Verilog, VHDL, Chisel, or SystemVerilog. [RTL abstraction and HDL expression]
Role in hardware fuzzing
NEIGHBORHOOD
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14 connectionsThe RTL design is compared with the ISA through formal equivalence proof.
The paper mentions RTL description as the design representation used in verification.
DirectFuzz operates on RTL designs and uses RTL-specific coverage feedback
The paper synthesizes rewrite rules from RTL descriptions of target architectures.
PORTRUSH operates at the register-transfer level to detect vulnerabilities in hardware designs.
RTL designs are the target of hardware fuzzing.
The ProcessorFuzz Tool operates on Register-Transfer Level designs.
Cadence JasperGold FPV supports RTL models for formal verification.
The architecture description is connected to the RTL implementation via mapping functions.
Mapping functions relate the architecture description to the RTL implementation.
Hardware fuzzing targets Register-Transfer Level designs.
Processor fuzzing operates at the Register Transfer Level for detecting vulnerabilities.
The equivalence proof is performed between the RTL implementation and the ISA.
RTL designs are expressed using hardware description languages
LINKED ENTITIES
4 linksHardware fuzzing topic_of RTL is the typical abstraction at which hardware-fuzzing research targets processor designs.
Hardware Description Language topic_of RTL designs are typically expressed in HDLs such as Verilog, VHDL, Chisel, and SystemVerilog.
formal verification topic_of RTL designs are a primary target for formal property verification and SEU evaluation.
Automatic Test Pattern Generation topic_of RTL functional-constraint extraction feeds pseudo-functional patterns to ATPG tools.
CITATIONS
16 sources16 citations — click to expand
[1] RTL designs are usually expressed in a hardware description language (HDL) such as Verilog, VHDL, Chisel, or SystemVerilog. Designing ML-Resilient Locking at Register-Transfer Level
[2] Hardware fuzzing targets RTL processor designs by mutating inputs in a feedback loop that rewards coverage of new hardware states. Designing ML-Resilient Locking at Register-Transfer Level
[3] ProcessorFuzz uses Control and Status Register (CSR) transitions as the coverage signal for fuzzing RTL designs and uses ISA-level simulation to rapidly determine interesting inputs. Designing ML-Resilient Locking at Register-Transfer Level
[4] ProcessorFuzz compares extended RTL trace logs with extended ISA trace logs and treats any difference as a potential processor-design bug. Designing ML-Resilient Locking at Register-Transfer Level
[5] The ProcessorFuzz evaluation used Verilator as an open-source RTL simulator and evaluated Chisel and SystemVerilog RISC-V processors, comparing against DIFUZZRTL. Designing ML-Resilient Locking at Register-Transfer Level
[6] RTL locking schemes operate earlier than gate-level netlist locking and have access to semantic hardware information, but ML attacks can exploit this semantic information. Designing ML-Resilient Locking at Register-Transfer Level
[7] A complete property suite can be automatically generated from an architecture description together with mapping functions for RTL signals, and used with IPC and OneSpin 360 MV to formally verify whole processor designs. Designing ML-Resilient Locking at Register-Transfer Level
[8] An automatic functional-constraint extractor operating at the register-transfer level produces functional constraints usable by ATPG tools, and the generated pseudo-functional test patterns improve the verification process. Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG
[9] Instiller is an RTL fuzzer based on a variant of Ant Colony Optimization (VACO) that distills input instructions and inserts interruptions and exceptions; it achieves 29.4% more coverage than DifuzzRTL, 17.0% more mismatches, and 79.3% shorter input instructions. Instiller: Toward Efficient and Realistic RTL Fuzzing | SCIENCE@home
[10] DifuzzRTL employs differential fuzz testing and a register-coverage metric tailored for RTL designs to guide input generation toward comprehensive CPU state exploration. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[11] FuSS uses selective symbolic execution to construct a minimal input sequence that activates rare scenarios dynamically, addressing coverage-plateau limitations of property-checking-based fuzzing approaches. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[12] DejaVuzz is a pre-silicon processor fuzzer for transient execution vulnerabilities at RTL, powered by dynamic swappable memory and differential information flow tracking primitives. DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
[13] Existing fuzzers use coverage metrics such as mux toggle coverage, control register coverage, and hardware behavior coverage; transient execution fuzzers like IntroSpectre, TEESec, and SpecDoctor analyze microarchitecture differently because general coverage metrics are unaware of sensitive-data propagation. DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
[14] DejaVuzz uses an RTL simulator to convert the Design Under Test (DUT) into a software model and uses instrumentation during simulation to measure coverage for guided mutations. DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
[15] Microarchitectural state transitions can be automatically extracted from a processor's RTL design and instrumented to monitor those transitions as coverage metrics for precise detection and localization of timing vulnerabilities. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[16] Cadence JasperGold FPV, a commercial formal verification tool that supports RTL models and SystemVerilog Assertions, is used with model checking on the RISC-V Ibex Core to exhaustively find candidate SEUs that may cause SDCs, crashes, and hangs. Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core