Register-Transfer Level

Concept

Register-Transfer Level (RTL) is described in the evidence as an abstraction for implementing hardware designs so they can be simulated and evaluated. RTL designs are usually expressed in hardware description languages such as Verilog or VHDL, and processor fuzzing workflows use RTL simulation and trace comparison against ISA simulation to identify potential processor bugs.

First seen 5/25/2026

Last seen 6/8/2026

Evidence 31 chunks

Wiki v3

WIKI

Overview

Register-Transfer Level (RTL) appears in the evidence as the abstraction used to implement hardware designs, including processors, for simulation-based evaluation. Unlike software programs, hardware is not directly executable on a host machine; instead, the hardware design is implemented with an RTL abstraction and simulated with an RTL simulator to evaluate a test input. RTL designs are usually expressed with a hardware description language (HDL), such as Verilog or VHDL. [RTL abstraction and HDL expression]

Role in processor fuzzing

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections

DirectFuzz ← uses 90% 2e

DirectFuzz operates on RTL designs and uses RTL-specific coverage feedback

Synthesizing Instruction Selection Rewrite Rules from RTL using SMT ← mentions 100% 2e

The paper synthesizes rewrite rules from RTL descriptions of target architectures.

Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← mentions 100% 2e

The paper mentions RTL description as the design representation used in verification.

Instruction Set Architecture ← compares with 90% 2e

The RTL design is compared with the ISA through formal equivalence proof.

Architecture Description ← uses 90% 1e

The architecture description is connected to the RTL implementation via mapping functions.

Mapping Functions ← uses 95% 1e

Mapping functions relate the architecture description to the RTL implementation.

hardware fuzzing ← uses 100% 1e

Hardware fuzzing targets Register-Transfer Level designs.

Equivalence Proof ← uses 100% 1e

The equivalence proof is performed between the RTL implementation and the ISA.

Hardware Description Language uses → 95% 1e

RTL designs are expressed using hardware description languages

LINKED ENTITIES

1 links

hardware fuzzing USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] RTL abstraction and HDL expression ProcessorFuzz: Processor Fuzzing with Control and

[2] RTL in hardware fuzzing ProcessorFuzz: Processor Fuzzing with Control and

[3] ISA versus RTL simulation ProcessorFuzz: Processor Fuzzing with Control and

[4] RTL and ISA trace comparison ProcessorFuzz: Processor Fuzzing with Control and

[5] RTL simulation tooling and comparison ProcessorFuzz: Processor Fuzzing with Control and