Equivalence Proof

Concept

An equivalence proof formally shows that two system descriptions exhibit the same relevant behavior under a defined relationship. In the cited processor-verification setting, the proof relates an RTL CPU implementation to an ISA-level model using an abstraction function from implementation state to architectural state.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

An equivalence proof is a formal argument that two descriptions of a system agree on the behavior of interest. In the processor-verification example from Generating an Efficient Instruction Set Simulator from a Complete Property Suite, the equivalence proof relates a CPU implementation at the Register Transfer Level (RTL) to an instruction-set architecture (ISA) model.

RTL-to-ISA structure

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← mentions 95% 2e

The paper describes the equivalence proof between the ISA and RTL as part of the verification.

The equivalence proof is performed between the RTL implementation and the ISA.

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite MENTIONS Extracted graph relationship

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[1] In the cited processor-verification setting, an equivalence proof relates RTL and ISA descriptions. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] The RTL-to-ISA proof uses an abstraction function vstate that maps CPU implementation state to ISA architectural state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The proof shows that applying the ISA next_state transition corresponds to applying the CPU transition relation and then mapping the resulting implementation state to the ISA state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] The proof also requires showing that interface signals match the interface macros and that the implementation reset state complies with the architectural reset state. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] A full equivalence proof between ISA and RTL is not required before generating the ISS; the ISS can be generated early from the ISA and full confidence is achieved later through verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] The architectural state is modeled explicitly, often as a VHDL record including components such as register file, status flags, and program counter, while next_state captures instruction and interrupt effects. Generating an Efficient Instruction Set Simulator from a Complete Property Suite