Hardware Description Language

Concept

A hardware description language (HDL) is a class of language used to express hardware designs at the Register-Transfer Level (RTL), with Verilog and VHDL cited as examples. In the cited processor-fuzzing evidence, HDL-based designs are evaluated through RTL simulation rather than direct host execution, and HDL choice can determine which verification tools and metrics are applicable. The cited evidence names Chisel and SystemVerilog as two HDLs in which open-source RISC-V processors are designed, and contrasts HDL-coupled fuzzers (RFUZZ, Li et al.) with HDL-agnostic ones (ProcessorFuzz).

First seen 5/28/2026

Last seen 6/8/2026

Evidence 11 chunks

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Overview

A hardware description language (HDL) is a language used to express hardware designs at the Register-Transfer Level (RTL). In the cited evidence, hardware (e.g., a processor) is not directly executable on a host machine; instead, a hardware design is implemented with an RTL abstraction and simulated with an RTL simulator to evaluate each test input. The RTL design is usually expressed with an HDL, with Verilog and VHDL given as examples. [C1][C2]

HDLs in processor verification

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

Chisel HDL mentions → 90% 2e

Chisel HDL is one of the Hardware Description Languages mentioned in the paper.

SystemVerilog HDL mentions → 90% 2e

SystemVerilog HDL is one of the Hardware Description Languages mentioned in the paper.

RTL designs are expressed using hardware description languages

ProcessorFuzz ← uses 90% 1e

ProcessorFuzz is agnostic to HDL and does not require HDL instrumentation

Chisel HDL ← part of 100% 1e

Chisel is one of the HDLs used in the evaluated processors.

SystemVerilog HDL ← part of 100% 1e

SystemVerilog is one of the HDLs used in the evaluated processors.

LINKED ENTITIES

2 links

Chisel HDL PART_OF Extracted graph relationship

SystemVerilog HDL PART_OF Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] A hardware design is implemented with an RTL abstraction and simulated with an RTL simulator to evaluate a test input, and the RTL design is usually expressed with an HDL (e.g., Verilog, VHDL). ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness

[2] ProcessorFuzz evaluates a variety of widely-used open-source RISC-V based processors designed in different HDLs (i.e., Chisel and SystemVerilog), and the Rocket Core RTL is shown as a representative HDL-based design. ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness

[3] RFUZZ and Li et al. are highly coupled to Chisel HDL which limits applicability; ProcessorFuzz is agnostic to HDL; Trippel et al. translate hardware designs to software models; TheHuzz relies on Cadence and ModelSim and software-style coverage metrics. ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness

[4] The fuzzing workflow applies differential testing between an RTL simulator running the HDL-based design and a reference model that is an ISA simulator, and ISA simulation is 79× faster than RTL simulation for the BOOM processor. ProcessorFuzz: Processor Fuzzing with Control and Status Register Awareness

[5] Veryl is a hardware description language based on SystemVerilog that provides optimized syntax for logic design, ensures synthesizability, prioritizes interoperability with SystemVerilog, and ships with development-support tools such as package managers and real-time checkers. Veryl: A New Hardware Description Language as an Alternative to SystemVerilog

[6] Board-level HDLs are explored to increase automation and raise the level of abstraction for electronics design, borrowing programming-language concepts such as generators and type systems while accounting for human factors. Opportunities and Challenges for Circuit Board Level Hardware Description Languages