Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
PaperFirst seen 6/8/2026
Last seen 6/8/2026
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50 connectionsThe paper introduces a method for synthesizing instruction selection rewrite rules from RTL.
The paper evaluates rewrite rule synthesis for CGRA processing elements.
The paper discusses synthesizing rewrite rules for RISC-V pseudo-operations.
The paper formalizes architectures as SMT formula tuples.
The paper evaluates synthesis of rewrite rules from WebAssembly to RISC-V.
The paper discusses register files as programmable states in architecture formalization.
The paper discusses encoding instructions as algebraic data types.
The paper supports floating-point operations through uninterpreted functions abstraction.
The paper motivates rewrite rule synthesis as enabling design space exploration.
The paper targets CGRA processing elements for rewrite rule synthesis.
The paper is motivated by and contributes to the code generation stage of compilers.
The paper targets instruction set architectures for rewrite rule synthesis.
Instruction selection is the core problem the paper addresses.
The paper uses intermediate representations as the source for rewrite rule synthesis.
The paper synthesizes rewrite rules from RTL descriptions of target architectures.
The paper uses WebAssembly as a source intermediate representation for rewrite rule synthesis.
The paper uses SMT solvers to synthesize rewrite rules.
The paper evaluates rewrite rule synthesis for the RV32I base RISC-V ISA.
The paper discusses pipelining as a challenge and possible future direction.
The paper introduces a technique for supporting parametric rewrite rules.
The paper evaluates rewrite rule synthesis for the RV32IM ISA.
Ross Daly is listed as an author of the paper.
The paper evaluates synthesis of floating-point rewrite rules using bfloat16.
The paper discusses Syntax-Guided Synthesis as a related technique and potential future work.
The paper compares its approach to the SKETCH program synthesis system.
The paper arose in the context of the Agile Hardware Project.
The paper mentions using VTR for place and route in design space exploration.
The paper mentions SMT-LIB as the language used by SyGuS.
The paper uses the SMT-LIB theory of bitvectors for formal analysis.
The paper formulates rewrite rule synthesis as an exists-forall problem.
The paper uses formal correctness criteria and discusses formal verification aspects.
The paper uses an 8-bit ALU as an example architecture.
The paper compares its approach to the work of Dias and Ramsey on rewrite rule synthesis.
The paper compares its approach to the work of Dias and Ramsey on rewrite rule synthesis.
The paper compares its approach to the work of Buchwald, Fried, and Hack.
The paper compares its approach to the work of Buchwald, Fried, and Hack.
The paper compares its approach to the work of Buchwald, Fried, and Hack.
The paper evaluates rewrite rule synthesis for the RV32IF ISA.
Caleb Donovick is listed as an author of the paper.
Jackson Melchert is listed as an author of the paper.
Rajsekhar Setaluri is listed as an author of the paper.
Nestan Tsiskaridze Bullock is listed as an author of the paper.
Priyanka Raina is listed as an author of the paper.
Clark Barrett is listed as an author of the paper.
Pat Hanrahan is listed as an author of the paper.
All authors are affiliated with Stanford University.
The paper uses Boolector as its SMT solver.
The paper uses pysmt to specify IRs directly in SMT.
The paper implements architectures in the Magma hardware description language.
The paper uses the hwtypes library associated with Magma for formal analysis.