8-bit ALU

Concept

An 8-bit arithmetic logic unit (ALU) is a data-path component that performs arithmetic and logical operations on 8-bit-wide operands. The available evidence documents two distinct contexts in which 8-bit ALUs appear: a physical superconducting ERSFQ parallel 8-bit ALU (designed, fabricated and tested at multi-GHz clock rates) and 8-bit bitvector (BV[8]) operations used as illustrative examples in SMT-based instruction selection rewrite-rule synthesis.

First seen 6/8/2026

Last seen 6/8/2026

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8-bit ALU

Overview

An 8-bit arithmetic logic unit (ALU) is a digital data-path component that performs arithmetic and logical operations on 8-bit-wide operands. The available evidence documents two distinct contexts in which 8-bit ALUs appear:

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Synthesizing Instruction Selection Rewrite Rules from RTL using SMT ← mentions 90% 1e

The paper uses an 8-bit ALU as an example architecture.

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CITATIONS

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[1] A parallel 8-bit ERSFQ ALU employs wave-pipelined instruction execution and a modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling, with a carry signal synchronised with asynchronous instruction propagation. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[2] The 8-bit ERSFQ ALU instruction set consists of 14 arithmetical and logical instructions, and the design was simulated for operation up to a 10 GHz clock rate at the 10-kA/cm² fabrication process. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[3] The 8-bit ERSFQ ALU is embedded into a shift-register-based high-frequency testbed with an on-chip clock generator to allow comprehensive high-frequency testing for all possible operands. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[4] The 8-bit ERSFQ ALU comprises 6840 Josephson junctions, fabricated with the MIT Lincoln Lab 10-kA/cm² SFQ5ee process featuring eight Nb wiring layers and a high-kinetic-inductance layer needed for ERSFQ technology. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[5] At low frequency the ERSFQ 8-bit ALU exhibited bias margins of ±11% for the clock and ±9% for instruction propagation, and correct functionality for all arithmetical and logical instructions with ±6% bias margins. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[6] The 8-bit ALU was tested for all instructions up to 2.8 GHz clock frequency. ERSFQ 8-bit Parallel Arithmetic Logic Unit

[7] An 8-bit adder with two BV[8] inputs x1, x2 is represented as (x1 +[8] x2, (0 ◦ x1 +[9] 0 ◦ x2)[8 : 8]), giving sum and carry-out; for input (11111111, 00000001) the outputs are 00000000 and 1. Synthesizing Instruction Selection Rewrite Rules from RTL using SMT

[8] A multifunction 8-bit ALU architecture Arch selects between subtraction, addition, multiplication, and division over BV[8] operands y1, y2 based on a 2-bit instruction field inst with encodings 00/01/10/11. Synthesizing Instruction Selection Rewrite Rules from RTL using SMT