pipelining

Concept

In the supplied processor-verification evidence, pipelining is treated as a micro-architecture-specific optimization that a co-simulation setup should be decoupled from. The evidence also identifies VexRiscv as a configurable, four-stage pipelined RISC-V RTL core used as the device under test in a coverage-guided fuzzing case study.

First seen 5/25/2026

Last seen 6/8/2026

Evidence 17 chunks

Wiki v2

WIKI

Overview

In the provided evidence, pipelining appears in the context of cross-level processor verification. The evidence characterizes pipelining as a micro-architecture-specific optimization: it is not the behavior being specified directly, but an implementation detail that can affect how an RTL processor core consumes an instruction stream during co-simulation.

Role in cross-level processor verification

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

8 connections

VexRiscv ← implements 100% 3e

VexRiscv is a 4-stage pipelined RTL-core.

Translation Buffer ← uses 90% 2e

The Translation Buffer helps decouple the co-simulation from pipelining-related micro-architecture specifics.

Synthesizing Instruction Selection Rewrite Rules from RTL using SMT ← mentions 90% 2e

The paper discusses pipelining as a challenge and possible future direction.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← mentions 90% 1e

The paper mentions pipelining as a modern processor feature that adds verification complexity.

MINRES The Good Core (TGC) Series ← uses 90% 1e

The TGC series processor uses pipelining as a micro-architectural feature.

MINRES The Good Core (TGC) ← implements 100% 1e

TGC is a pipelined processor

RISC-V part of → 85% 1e

RISC-V processors can include pipelining as micro-architectural optimization

Core Adapter ← uses 90% 1e

The Core-Adapter handles pipelining-related fetch behavior differences between ISS and RTL core.

LINKED ENTITIES

1 links

VexRiscv IMPLEMENTS Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Pipelining is treated as a micro-architecture-specific optimization in the co-simulation approach. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] The Translation Buffer transforms bounded fuzzer-generated test vectors into deterministic endless instruction streams through cyclic repetition and helps decouple co-simulation from optimizations such as pipelining. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] The co-simulation combines an RTL core under test with a reference ISS, and an execution controller checks equality through register-value comparison. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] VexRiscv is used as the device under test and is described as a configurable four-stage pipelined RISC-V RTL core written in SpinalHDL. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] The evaluation uses the RV32IM configuration of VexRiscv and a reference ISS extracted from the open-source RISC-V VP. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing