Translation Buffer
CodeArtifactThe Translation Buffer is a co-simulation component for coverage-guided processor verification that converts a bounded fuzzer-generated test vector into a deterministic endless instruction stream. It is implemented as a customized ring-buffer-like structure that supports cyclic reading, enabling an RTL core and a reference instruction set simulator to consume the same instruction stream despite differences such as RTL pipelining.
WIKI
Overview
The Translation Buffer is an essential component in a cross-level processor verification co-simulation setup. In the described flow, a coverage-guided fuzzer generates bounded test vectors, and the Translation Buffer transforms those vectors into an endless instruction stream for execution by both the RTL core under test and a reference instruction set simulator (ISS). This supports co-simulation of the RTL core and ISS while helping decouple the setup from micro-architecture-specific optimizations such as pipelining. [Translation Buffer role]
Purpose
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