Co-simulation

Concept

Co-simulation is a simulation approach in which multiple models or simulators are run together and coordinated so their behavior can be compared or combined. In processor verification, co-simulation typically couples a design under test (DUT) with a golden reference model, most often an Instruction Set Simulator (ISS), so the two implementations execute the same test program and generate per-instruction execution traces that are compared. Synchronization between the DUT and reference can be achieved with Direct Programming Interface (DPI) calls, by monitoring microarchitectural structures such as the reorder buffer, or by injecting instructions through RVFI-based interfaces. The REF is typically retained in software for flexibility, while the DUT may be deployed through software-based RTL simulation or on hardware acceleration platforms. Hardware-accelerated setups are dominated by communication overhead, which has motivated techniques such as DiffTest-H's Batch, Squash, and Replay that reduce communication frequency, transmission volume, and preserve debuggability. Co-simulation has also been specialized for processor fuzzing (e.g., MorFuzz's synchronizable and delayed-write-back-tolerant co-simulation), coverage-guided randomized instruction generation, distributed FMI-based modeling with IP protection, and cyber-security analysis of power systems.

First seen 5/25/2026

Last seen 6/8/2026

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Co-simulation

Overview

Co-simulation is a simulation approach in which multiple models or simulators are run together and coordinated so their behavior can be compared or combined. In processor verification, a co-simulation framework runs a design under test (DUT) and a golden reference model (REF) side by side on the same test program, generates execution traces for each instruction, and compares them; if the traces differ, the cause must be investigated because the mismatch may indicate a bug. In other domains, co-simulation is used to couple heterogeneous simulators or to distribute simulation across networked platforms.

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RELATIONSHIPS

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 11e

The paper leverages ISS and RTL in a tight co-simulation setting.

Dromajo ← implements 100% 4e

Dromajo is designed specifically for co-simulation with RTL processors.

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← uses 100% 4e

The paper uses co-simulation as a central verification technique.

Cross-Level Processor Verification ← uses 95% 4e

Cross-level processor verification uses co-simulation with an ISS as reference model.

RISC-V Design Verification (DV) Framework ← uses 90% 3e

RISC-V DV leverages co-simulation with an ISS as reference model.

Instruction Set Simulator (ISS) uses → 100% 3e

Co-simulation integrates the ISS with the RTL core.

DiffTest ← uses 100% 2e

DiffTest is a co-simulation framework for processor verification.

UVM Based Design Verification of a RISC-V CPU Core ← uses 90% 2e

The paper employs co-simulation methodology using Spike as a reference model.

Co-simulation combines ISS with the RTL processor core for comparison.

UVM environment ← uses 98% 2e

The UVM environment performs step-by-step co-simulation of all vector instructions.

Synchronizable Co-simulation ← implements 100% 2e

Synchronizable co-simulation is a specific implementation of co-simulation that handles implementation differences.

MorFuzz ← implements 100% 2e

MorFuzz implements a synchronizable co-simulation framework.

DiffTest-H ← uses 100% 2e

DiffTest-H is a hardware-accelerated co-simulation framework.

UVM ← implements 95% 2e

The UVM environment performs step-by-step co-simulation of all vector instructions with Spike.

sail-riscv uses → 1e

Co-simulation in RISCV-DV uses sail-riscv as one of the supported ISS tools.

Comparator ← uses 85% 1e

The Comparator compares register values between the ISS and RTL-Core in the co-simulation setup.

Google RISC-V Design Verification (DV) Framework ← uses 90% 1e

Google DV framework employs co-simulation with an ISS.

whisper ← implements 90% 1e

Whisper is an ISS developed by Western Digital that can be used for co-simulation.

Comparator ← uses 90% 1e

The Comparator works within a co-simulation setting to compare ISS and RTL core register values.

Ibex Core ← uses 100% 1e

Ibex verification employs a co-simulation methodology.

Comparator ← part of 90% 1e

The Comparator is used to find functional differences between RTL-Core and ISS.

UVM testbench ← uses 95% 1e

The UVM testbench performs co-simulation of vector instructions against Spike.

Core Adapter ← part of 90% 1e

The Core-Adapter is used in the co-simulation to handle micro-architectural differences.

Simulation-based Processor Verification ← uses 90% 1e

Simulation-based verification leverages co-simulation with ISS as a reference model.

Reference Model uses → 95% 1e

Co-simulation relies on a reference model to compare DUT outputs.

Design Under Test uses → 100% 1e

Co-simulation runs the design-under-test in parallel with a reference model.

Architectural State uses → 100% 1e

Co-simulation compares the architectural state of the DUT and the model.

golden model uses → 100% 1e

Co-simulation compares the DUT against the golden model.

riscv-dv ← implements 1e

RISCV-DV implements co-simulation with multiple instruction set simulators.

spike uses → 1e

Co-simulation in RISCV-DV uses spike as one of the supported ISS tools.

riscv-ovpsim uses → 1e

Co-simulation in RISCV-DV uses riscv-ovpsim as one of the supported ISS tools.

whisper uses → 1e

Co-simulation in RISCV-DV uses whisper as one of the supported ISS tools.

LINKED ENTITIES

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DPI-based Synchronization USES Extracted graph relationship

Reorder Buffer Monitoring USES Extracted graph relationship

CITATIONS

15 sources

15 citations — click to expand

[1] Dromajo is an ISS used as the golden model in a co-simulation setup that verified three RISC-V processors and relies on Direct Programming Interface (DPI) calls to synchronize the implementations. Large-Scale RISC-V Processor Verification Using Automated ...

[2] In the Dromajo-based co-simulation, the processor code is modified to monitor the reorder buffer and to invoke the ISS at each commit as the instruction-completion detection mechanism. Large-Scale RISC-V Processor Verification Using Automated ...

[3] Five additional processors were verified using RVFI-Direct Instruction Injection (RVFI-DII), an extension of the RISC-V Formal Interface that injects instructions directly into the processor's fetch interface. Large-Scale RISC-V Processor Verification Using Automated ...

[4] RVFI-DII requires highly processor-specific code; for example, the Flute in-order scalar core used an instruction ID attached to the program counter that was propagated through each stage of the pipeline. Large-Scale RISC-V Processor Verification Using Automated ...

[5] The RISC-V Formal Framework defines a generic interface, RVFI, which has been adopted as a standard trace format for verifying cores via co-simulation. Large-Scale RISC-V Processor Verification Using Automated ...

[6] Synopsys ImperasDV is a commercial verification suite for RISC-V processors that provides reference-model comparison and coverage analysis, and defines a generic interface called the RISC-V Verification Interface (RVVI). Large-Scale RISC-V Processor Verification Using Automated ...

[7] The CVA6 core was verified using the Dromajo-based approach in 280 lines of code, the Ibex core required more than 450 lines of code when verified using RVFI-DII, and the cited verification solution required 270 lines of code to verify Hazard3. Large-Scale RISC-V Processor Verification Using Automated ...

[8] Both cited RISC-V verification studies depend on modifying microarchitecture-specific structures: Ibex had its pipeline stages modified to implement the RVFI-DII interface, and CVA6 had its reorder buffer modified. Large-Scale RISC-V Processor Verification Using Automated ...

[9] In the cited large-scale RISC-V verification work, six processors needed an adapter module: Hazard3 used an AHB-to-Wishbone adapter; RVX, Kronos, and RS5 required a Wishbone-to-Pipelined-Wishbone adapter that introduced a one-cycle data delay. Large-Scale RISC-V Processor Verification Using Automated ...

[10] The hardware-accelerated platforms in processor co-simulation speed up DUT simulation by 300×–10000×, but overall co-simulation speedup is still limited to 2.5×–20× because more than 98% of co-simulation time is consumed by communication overhead. Large-Scale RISC-V Processor Verification Using Automated ...

[11] The Cadence Palladium emulator performs hardware-software synchronization at every DPI-C function call as part of the communication-startup stage in the LogGP overhead model. Large-Scale RISC-V Processor Verification Using Automated ...

[12] MorFuzz applies an online co-simulation approach for state verification, using an ISA simulator running in parallel with the DUT as the reference model, and uses a synchronizable co-simulation component to synchronize legal differences between models. Large-Scale RISC-V Processor Verification Using Automated ...

[13] MorFuzz abstracts the state comparison process into a commitment stage and a judgment stage to accommodate microarchitectural features such as delayed write-back in cores like Rocket. Large-Scale RISC-V Processor Verification Using Automated ...

[14] Distributed co-simulation has been used as a mechanism for collaborative modeling and simulation while implicitly helping protect intellectual property; FMI-based distributed co-simulation on top of UniFMU has been proposed with additional cybersecurity and IP-protection mechanisms. FMI-Based Distributed Co-Simulation with Enhanced Security and Intellectual Property Safeguards

[15] Co-simulation has been used for cyber-security analysis of power systems, coupling DIgSILENT PowerFactory, OMNeT++, and Matlab to simulate data attacks against energy management systems. Co-simulation for Cyber Security Analysis: Data Attacks against Energy Management System