Spike
ToolSpike is an open-source RISC-V instruction-set simulator (ISS) developed by the RISC-V Foundation that serves as the de facto reference model for the RISC-V ISA. It is used in RTL co-simulation, functional verification, and as a golden reference for CPU verification, including through tools such as RISCV-DV.
First seen 5/25/2026
Last seen 9/5/2026
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WIKI
Spike
Spike is an open-source instruction-set simulator (ISS) for the RISC-V Instruction Set Architecture (ISA). It is developed and maintained under the RISC-V Foundation / RISC-V Software organization, and acts as a reference model of the RISC-V ISA. The official source repository is https://github.com/riscv-software-src/riscv-isa-sim.
Role and characteristics
NEIGHBORHOOD
8 nodes · 22 edgesgraph · spike · depth=1
RELATIONSHIPS
50 connectionsTestRIG added Direct Instruction Injection to Spike emulator to use it as a reference implementation.
Spike can serve as a reference model and supports adding new custom instruction behaviour.
Spike serves as the de-facto golden reference model for RISC-V
The paper describes using Spike as the reference model for co-simulation.
spike is an open source ISS for RISC-V
Spike is evaluated with SoftFloat as its FP backend integration.
The paper evaluates Spike as a reference ISS and finds an error in it.
SPIKE is the official RISC-V reference ISS
riscv-dv uses Spike as a reference ISS for comparing execution results.
FP-RVVTS evaluates Spike as a DUT in its verification flow.
Spike is a RISC-V ISA simulator.
MorFuzz uses the spike ISA simulator as the reference model for co-simulation.
Spike is the official RISC-V ISA reference simulator implementing the RISC-V ISA.
Cascade uses Spike as its ISS for asymmetric pre-simulation
Spike is used as the RISC-V ISA simulator reference in Prelude.
RVVTS uses Spike as the reference simulator for co-simulation and architectural state comparison.
Spike is a high-performance RISC-V emulator.
Spike is the official RISC-V golden reference simulator maintained by RISC-V International.
GenHuzz uses Spike as the RISC-V ISA reference model (Golden Reference Model) for differential testing.
Prior verification efforts for Ara used co-simulation with Spike.
The paper evaluates Spike simulator for compliance testing.
HARTBREAKER uses Spike as a golden model ISS.
HiFuzz uses Spike as the reference model for differential testing on RISC-V cores.
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e
The paper evaluates the approach using Spike as one of the target simulators
The UVM environment uses Spike as its reference model for co-simulation.
CHIA uses Spike as the golden ISA simulator oracle for differential verification throughout the flow.
Spike is the official RISC-V reference simulator.
EAVS uses Spike as its ISS/golden model component.
Prelude uses Spike as the ISA simulator reference model for differential testing.
The encoding.h header file is used by Spike.
LiFU uses Spike ISS as a golden oracle for differential testing.
Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior ← evaluates 100% 2e
The paper evaluates Spike as golden reference model for comparison
Sail-RISC-V is compared against Spike as golden reference
RISCSmith uses Spike as the golden reference model for differential comparison.
Spike is used as the reference ISA simulator for co-simulation
Spike is evaluated with FloppyFloat as its FP backend integration.
FP-RVVTS uses Spike as the golden reference simulator.
CFC uses Spike as the software model for co-simulation.
CFC uses Spike as the software model for RISC-V co-simulation.
Spike provides an instruction-accurate functional model of RISC-V cores.
Spike supports a Gemmini extension for processing custom Gemmini instructions.
Spike has been widely used in architectural validation flows
Spike's handling of unordered floating-point reductions required special workarounds.
Co-simulation in RISCV-DV uses spike as one of the supported ISS tools.
Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.
The synchronizable co-simulation uses Spike as the reference model.
Spike is a RISC-V ISA simulator implementing the RISC-V ISA.
The unordered floating-point reduction reference model is used instead of Spike for non-deterministic reduction results.
Spike is adapted to follow the RISC-V vector specification 0.7.1
The scoreboard directly takes information from Spike as reference
LINKED ENTITIES
2 linksCITATIONS
6 sources6 citations — click to expand
[1] Spike is an open-source ISS for the RISC-V ISA, developed by the RISC-V Foundation, supporting official extensions, exceptions, interrupts, and a debugging mode. Reinforcement Learning Framework for RISC-V Functional Verification
[2] The official Spike repository is at github.com/riscv-software-src/riscv-isa-sim and Spike is used as a reference RISC-V ISS in the CHIPS Alliance / SV Tools Project co-simulation workflow. CHIPS Alliance SV Tools Project announcement
[3] RISCV-DV supports co-simulation with multiple ISSes including spike, riscv-ovpsim, whisper, and sail-riscv, comparing architectural state after each executed instruction. RISCV-DV overview (OpenSecura match-a tree)
[4] In RISC-V core verification flows, Spike is used as the golden reference ISS: its output is parsed for data-memory transactions that feed a scoreboard, and a write to address 0x20008 with value 1 is used to drop the UVM objection and end simulation. Reinforcement Learning Framework for RISC-V Functional Verification
[5] Spike (or QEMU) is the typical golden reference ISS used in RISC-V functional verification, where DUT architectural state must match the reference after each instruction. Inside RISC-V: Navigating the RTL Design & Verification Landscape
[6] In coverage-guided fuzzing of RISC-V ISSs, a coverage-guided run on Spike was reported to find a Spike issue labeled S1, achieving 100% branch coverage and 100% in R1/R2/R3 functional coverage columns; the run took 32,492 seconds. Reinforcement Learning Framework for RISC-V Functional Verification