Spike
ToolSpike is an open-source RISC-V instruction-set simulator (ISS) developed by the RISC-V Foundation that serves as the de facto reference model for the RISC-V ISA. It is used in RTL co-simulation, functional verification, and as a golden reference for CPU verification, including through tools such as RISCV-DV.
First seen 5/25/2026
Last seen 7/19/2026
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WIKI
Spike
Spike is an open-source instruction-set simulator (ISS) for the RISC-V Instruction Set Architecture (ISA). It is developed and maintained under the RISC-V Foundation / RISC-V Software organization, and acts as a reference model of the RISC-V ISA. The official source repository is https://github.com/riscv-software-src/riscv-isa-sim.
Role and characteristics
NEIGHBORHOOD
16 nodes · 38 edgesgraph · spike · depth=1
RELATIONSHIPS
50 connectionsTestRIG added Direct Instruction Injection to Spike emulator to use it as a reference implementation.
Spike acts as the reference model in the verification environment, predicting expected instruction results.
Spike acts as the Golden Reference Model implementation for RISC-V in GoldenFuzz.
The paper describes using Spike as the reference model for co-simulation.
The paper evaluates Spike as a reference ISS and finds an error in it.
Spike implements the Instruction Set Simulator concept for RISC-V.
RISCV-DV uses spike as an ISS for co-simulation
Spike uses SoftFloat as its underlying FP library.
Spike is a high-performance RISC-V emulator.
Spike is the official RISC-V golden reference simulator maintained by RISC-V International.
MorFuzz uses the spike ISA simulator as the reference model for co-simulation.
Spike is the official RISC-V ISA reference simulator implementing the RISC-V ISA.
Cascade uses Spike as its ISS for asymmetric pre-simulation
Spike is the RISC-V ISA simulator used as the Golden Reference Model.
FP-RVVTS uses Spike as the golden reference simulator.
Spike is the official RISC-V reference simulator.
EAVS uses Spike as its ISS/golden model component.
Spike is an implementation of an Instruction Set Simulator for RISC-V.
Spike is used as the reference ISA simulator for co-simulation
RISCSmith uses Spike as the golden reference model for differential comparison.
GenHuzz uses Spike as the RISC-V ISA reference model (Golden Reference Model) for differential testing.
The UVM environment uses Spike as its reference model for co-simulation.
HARTBREAKER uses Spike as a golden model ISS.
HiFuzz uses Spike as the reference model for differential testing on RISC-V cores.
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e
The paper evaluates the approach using Spike as one of the target simulators
FP-RVVTS uses Spike as its golden reference model and evaluates other simulators against it.
XiangShan supports Spike as an alternative golden reference model.
cov.py processes spike simulation output for coverage
run.py can invoke spike for ISS simulation
RVVTS uses Spike as the golden reference model for execution comparison.
RefCovRunner uses Spike as an Execution Runner to provide Machine State.
Spike acts as the golden model reference for verifying RISC-V core execution.
Spike's handling of unordered floating-point reductions required special workarounds.
Co-simulation in RISCV-DV uses spike as one of the supported ISS tools.
Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.
The synchronizable co-simulation uses Spike as the reference model.
Spike is a RISC-V ISA simulator implementing the RISC-V ISA.
The unordered floating-point reduction reference model is used instead of Spike for non-deterministic reduction results.
Spike is adapted to follow the RISC-V vector specification 0.7.1
The scoreboard directly takes information from Spike as reference
The paper incorporates Spike as a RISC-V ISS for co-simulation validation.
Ibex Core verification uses Spike as a golden ISS reference model for co-simulation.
Spike FF is a modified, performance-tuned version of the official Spike simulator.
Spike has a decoder error that was found by the fuzzer.
The UVM environment uses Spike as a reference model for co-simulation of vector instructions.
Spike was adapted to support the RISC-V Vector extension version 0.7.1 specification.
Spike has been extended with the Direct Instruction Injection interface for use with TestRIG.
TestRIG evaluates Spike as a RISC-V implementation.
The paper evaluates the complete CT infrastructure on SPIKE.
NEMU is described as similar to Spike, both being instruction set simulators.
LINKED ENTITIES
2 linksCITATIONS
6 sources6 citations — click to expand
[1] Spike is an open-source ISS for the RISC-V ISA, developed by the RISC-V Foundation, supporting official extensions, exceptions, interrupts, and a debugging mode. Reinforcement Learning Framework for RISC-V Functional Verification
[2] The official Spike repository is at github.com/riscv-software-src/riscv-isa-sim and Spike is used as a reference RISC-V ISS in the CHIPS Alliance / SV Tools Project co-simulation workflow. CHIPS Alliance SV Tools Project announcement
[3] RISCV-DV supports co-simulation with multiple ISSes including spike, riscv-ovpsim, whisper, and sail-riscv, comparing architectural state after each executed instruction. RISCV-DV overview (OpenSecura match-a tree)
[4] In RISC-V core verification flows, Spike is used as the golden reference ISS: its output is parsed for data-memory transactions that feed a scoreboard, and a write to address 0x20008 with value 1 is used to drop the UVM objection and end simulation. Reinforcement Learning Framework for RISC-V Functional Verification
[5] Spike (or QEMU) is the typical golden reference ISS used in RISC-V functional verification, where DUT architectural state must match the reference after each instruction. Inside RISC-V: Navigating the RTL Design & Verification Landscape
[6] In coverage-guided fuzzing of RISC-V ISSs, a coverage-guided run on Spike was reported to find a Spike issue labeled S1, achieving 100% branch coverage and 100% in R1/R2/R3 functional coverage columns; the run took 32,492 seconds. Reinforcement Learning Framework for RISC-V Functional Verification