Spike

Tool

Spike is a RISC-V instruction-set architecture simulator identified in the evidence as the official RISC-V reference simulator. A coverage-guided fuzzing study for instruction-set simulator verification evaluated Spike alongside other public RISC-V ISSs and reported that the fuzzing run found one Spike issue, labeled S1.

First seen 5/25/2026

Last seen 6/9/2026

Evidence 39 chunks

Wiki v6

WIKI

Spike

Spike is a RISC-V instruction-set architecture (ISA) simulator. The evidence identifies it as the “Spike RISC-V ISA simulator” and also refers to it as the official RISC-V reference simulator. Two cited repository locations appear in the provided sources: https://github.com/riscv/riscv-isa-sim in the ISS-fuzzing paper and https://github.com/riscv-software-src/riscv-isa-sim in a later bibliography.

Role in ISS verification

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NEIGHBORHOOD

5 nodes · 7 edges

graph · spike · depth=1

RELATIONSHIPS

33 connections

TestRIG ← uses 100% 12e

TestRIG added Direct Instruction Injection to Spike emulator to use it as a reference implementation.

Reference Model implements → 99% 8e

Spike acts as the reference model in the verification environment, predicting expected instruction results.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← evaluates 100% 6e

The paper evaluates Spike as a reference ISS and finds an error in it.

Functional Verification of a RISC-V Vector Accelerator ← uses 99% 6e

The paper describes using Spike as the reference model for co-simulation.

MorFuzz ← uses 100% 3e

MorFuzz uses the spike ISA simulator as the reference model for co-simulation.

Instruction Set Architecture implements → 100% 3e

Spike is the official RISC-V ISA reference simulator implementing the RISC-V ISA.

RISC-V implements → 100% 3e

Spike is a high-performance RISC-V emulator.

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e

The paper evaluates the approach using Spike as one of the target simulators

UVM ← uses 97% 2e

The UVM environment uses Spike as its reference model for co-simulation.

Co-Simulation ← uses 99% 2e

Spike is used as the reference ISA simulator for co-simulation

riscv-dv ← uses 90% 2e

RISCV-DV tests are executed on Spike simulator for trace measurement.

ElectraIC Advanced Verification Suite (EAVS) ← uses 2e

EAVS uses Spike as its ISS/golden model component.

Instruction Set Simulator implements → 100% 2e

Spike is an instruction set simulator implementing the RISC-V ISA.

UVM environment ← uses 98% 1e

The UVM environment uses Spike as a reference model for co-simulation of vector instructions.

RISC-V Vector extension uses → 95% 1e

Spike was adapted to support the RISC-V Vector extension version 0.7.1 specification.

RVFI-DII implements → 95% 1e

Spike has been extended with the Direct Instruction Injection interface for use with TestRIG.

NEMU ← compares with 95% 1e

NEMU is described as similar to Spike, both being instruction set simulators.

Instruction Set Simulator (ISS) implements → 1e

Spike implements the Instruction Set Simulator concept for RISC-V.

golden model implements → 1e

Spike acts as the golden model reference for verifying RISC-V core execution.

RISC-V International Foundation published by → 1e

Spike is officially released by the RISC-V International Foundation.

Ibex Core ← uses 100% 1e

Ibex Core verification uses Spike as a golden ISS reference model for co-simulation.

RISC-V ISA implements → 97% 1e

Spike is the RISC-V ISA simulator that implements the RISC-V ISA for simulation purposes.

Unordered Floating-Point Reductions uses → 85% 1e

Spike's handling of unordered floating-point reductions required special workarounds.

Co-simulation ← uses 1e

Co-simulation in RISCV-DV uses spike as one of the supported ISS tools.

RVFI-DII uses → 95% 1e

Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.

Synchronizable Co-simulation ← uses 100% 1e

The synchronizable co-simulation uses Spike as the reference model.

RISC-V ISA uses → 97% 1e

Spike is a RISC-V ISA simulator implementing the RISC-V ISA.

unordered floating-point reduction reference model ← compares with 93% 1e

The unordered floating-point reduction reference model is used instead of Spike for non-deterministic reduction results.

RISC-V Vector extension (RVV) uses → 97% 1e

Spike is adapted to follow the RISC-V vector specification 0.7.1

UVM scoreboard ← uses 98% 1e

The scoreboard directly takes information from Spike as reference

UVM Based Design Verification of a RISC-V CPU Core ← uses 100% 1e

The paper incorporates Spike as a RISC-V ISS for co-simulation validation.

instruction set simulation implements → 98% 1e

Spike is a RISC-V ISA simulator used for instruction set simulation.

Instruction Decoder mentions → 95% 1e

Spike has a decoder error that was found by the fuzzer.

LINKED ENTITIES

2 links

Verifying Instruction Set Simulators using Coverage-guided Fuzzing EVALUATES Extracted graph relationship

Instruction Set Architecture IMPLEMENTS Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Spike is identified as a RISC-V ISA simulator and as the official RISC-V reference simulator. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[2] The provided sources cite Spike repository URLs at https://github.com/riscv/riscv-isa-sim and https://github.com/riscv-software-src/riscv-isa-sim. Bibliography containing Spike repository citation

[3] The coverage-guided fuzzing paper evaluated Spike as one of three publicly available RISC-V ISSs and implemented its approach on top of LLVM libFuzzer with a functional coverage metric and ISS-specific mutation procedure. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[4] The paper reports finding new errors in every considered ISS, including one error in Spike. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[5] In the evaluation table, coverage-guided fuzzing found Spike issue S1, while the RISC-V ISA tests and RISC-V Torture runs showed no Spike issues. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[6] The table reports the coverage-guided fuzzing run as taking 32,492 seconds, reaching 100% branch coverage and 100% R1/R2/R3 functional coverage, and finding ISS-under-test errors [V1..V7], Spike issue S1, and Forvis issues H1,H2. Verifying Instruction Set Simulators using Coverage-guided Fuzzing