Spike
ToolSpike is an open-source RISC-V instruction-set simulator (ISS) developed by the RISC-V Foundation that serves as the de facto reference model for the RISC-V ISA. It is used in RTL co-simulation, functional verification, and as a golden reference for CPU verification, including through tools such as RISCV-DV.
First seen 5/25/2026
Last seen 9/20/2026
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Spike
Spike is an open-source instruction-set simulator (ISS) for the RISC-V Instruction Set Architecture (ISA). It is developed and maintained under the RISC-V Foundation / RISC-V Software organization, and acts as a reference model of the RISC-V ISA. The official source repository is https://github.com/riscv-software-src/riscv-isa-sim.
Role and characteristics
NEIGHBORHOOD
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50 connectionsTestRIG added Direct Instruction Injection to Spike emulator to use it as a reference implementation.
Spike can serve as a reference model and supports adding new custom instruction behaviour.
Spike serves as the golden-reference model for differential testing in processor fuzzing.
Spike is evaluated with SoftFloat as its FP backend integration.
The paper describes using Spike as the reference model for co-simulation.
Spike is a widely used open-source ISS for RISC-V.
spike is an open source ISS for RISC-V
The paper evaluates Spike as a reference ISS and finds an error in it.
Spike is the de facto standard RISC-V ISA simulator implementing the RISC-V ISA.
Cascade uses Spike as the ISS for asymmetric ISA pre-simulation.
riscv-dv uses Spike as a reference ISS for comparing execution results.
FP-RVVTS evaluates Spike as a DUT in its verification flow.
Spike is the official RISC-V ISA reference simulator implementing the RISC-V ISA.
RVVTS uses Spike as the reference simulator for co-simulation and architectural state comparison.
Spike is the official RISC-V golden reference simulator maintained by RISC-V International.
Spike is a high-performance RISC-V emulator.
Spike is used as the RISC-V ISA simulator reference in Prelude.
MorFuzz uses the spike ISA simulator as the reference model for co-simulation.
Spike is used as the reference ISA simulator for co-simulation
The UVM environment uses Spike as its reference model for co-simulation.
The paper evaluates Spike simulator for compliance testing.
Spike is a RISC-V ISS and therefore uses the RISC-V ISA.
FP-RVVTS uses Spike as the golden reference simulator.
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← evaluates 100% 2e
The paper evaluates the approach using Spike as one of the target simulators
Spike is the official RISC-V reference simulator.
EAVS uses Spike as its ISS/golden model component.
RISCSmith uses Spike as the golden reference model for differential comparison.
GenHuzz uses Spike as the RISC-V ISA reference model (Golden Reference Model) for differential testing.
HARTBREAKER uses Spike as a golden model ISS.
HiFuzz uses Spike as the reference model for differential testing on RISC-V cores.
CHIA uses Spike as the golden ISA simulator oracle for differential verification throughout the flow.
Prelude uses Spike as the ISA simulator reference model for differential testing.
The encoding.h header file is used by Spike.
LiFU uses Spike ISS as a golden oracle for differential testing.
Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior ← evaluates 100% 2e
The paper evaluates Spike as golden reference model for comparison
Sail-RISC-V is compared against Spike as golden reference
Spike is evaluated with FloppyFloat as its FP backend integration.
Prior verification efforts for Ara used co-simulation with Spike.
Asymmetric ISA pre-simulation uses Spike as the ISS for pre-simulation.
PySpike extends Spike by adding Python bindings through Spike's dlopen plugin system without modifying Spike's core code.
The synchronizable co-simulation uses Spike as the reference model.
Spike FF is a modified, performance-tuned version of the official Spike simulator.
Suresh Chips and Semiconductor uses Spike as a golden reference ISS for RISC-V verification.
Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.
Ibex Core verification uses Spike as a golden ISS reference model for co-simulation.
GoldenFuzz uses Spike as the ISA-compliant emulator (Golden Reference Model) for RISC-V processors.
The paper incorporates Spike as a RISC-V ISS for co-simulation validation.
Spike is used as a reference model for differential testing in hardware/software co-verification.
XiangShan supports Spike as an alternative golden reference model.
RISC-V VP uses SPIKE as a reference simulator for testing
LINKED ENTITIES
2 linksCITATIONS
6 sources6 citations — click to expand
[1] Spike is an open-source ISS for the RISC-V ISA, developed by the RISC-V Foundation, supporting official extensions, exceptions, interrupts, and a debugging mode. Reinforcement Learning Framework for RISC-V Functional Verification
[2] The official Spike repository is at github.com/riscv-software-src/riscv-isa-sim and Spike is used as a reference RISC-V ISS in the CHIPS Alliance / SV Tools Project co-simulation workflow. CHIPS Alliance SV Tools Project announcement
[3] RISCV-DV supports co-simulation with multiple ISSes including spike, riscv-ovpsim, whisper, and sail-riscv, comparing architectural state after each executed instruction. RISCV-DV overview (OpenSecura match-a tree)
[4] In RISC-V core verification flows, Spike is used as the golden reference ISS: its output is parsed for data-memory transactions that feed a scoreboard, and a write to address 0x20008 with value 1 is used to drop the UVM objection and end simulation. Reinforcement Learning Framework for RISC-V Functional Verification
[5] Spike (or QEMU) is the typical golden reference ISS used in RISC-V functional verification, where DUT architectural state must match the reference after each instruction. Inside RISC-V: Navigating the RTL Design & Verification Landscape
[6] In coverage-guided fuzzing of RISC-V ISSs, a coverage-guided run on Spike was reported to find a Spike issue labeled S1, achieving 100% branch coverage and 100% in R1/R2/R3 functional coverage columns; the run took 32,492 seconds. Reinforcement Learning Framework for RISC-V Functional Verification