RVFI-DII
ConceptRVFI-DII (pronounced "rividy") is the TestRIG-compatible combination of the RISC-V Formal Interface (RVFI) for per-instruction state observation and Direct Instruction Injection (DII) for harness-driven instruction supply. TestRIG vengines produce DII instruction traces and consume RVFI execution traces from implementations, comparing the etraces returned by a model and an implementation under test over a single socket to detect divergence.
First seen 5/27/2026
Last seen 8/11/2026
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Overview
RVFI-DII (pronounced "rividy") is the combined verification interface used by the TestRIG framework. It joins the RISC-V Formal Interface (RVFI), a tracing protocol for RISC-V processors that specifies the results of running instructions, with Direct Instruction Injection (DII), in which the next instruction is supplied by the test harness rather than fetched from program memory. TestRIG describes itself as "a framework for RISC-V processor verification using the RVFI-DII interface," and the full wire format is documented in the project repository's RVFI-DII specification.
Components and data flow
NEIGHBORHOOD
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correctness.","confidence":0.99},{"src_label":"Concept","src_name":"Vengine","relation_type":"USES","dst_label":"Concept","dst_name":"RVFI-DII","evidence_chunk_ids":["2d1a953c-bbc5-45f5-957a-56c3d6263029"],"quote":"The vengine then feeds these itraces into both a model and an implementation through two TCP sockets in the RVFI-DII format.","claim":"Vengines communicate with implementations using the RVFI-DII format.","description":"Vengines use the RVFI-DII protocol over TCP sockets to communicate instruction and execution traces.","confidence":0.99},{"src_label":"Tool","src_name":"QuickCheck Verification Engine","relation_type":"IMPLEMENTS","dst_label":"Concept","dst_name":"Vengine","evidence_chunk_ids":["42f69dc2-1bc8-4247-b342-561f49596e0a"],"quote":"The root makefile can currently build the QuickCheck Verification Engine, Spike, and the Sail implementation.","claim":"The QuickCheck Verification Engine is an implementation of the Vengine concept in TestRIG.","description":"The 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The paper introduces RVFI-DII as a combined interface for instruction injection and trace output.
Toooba is instrumented with RVFI-DII for use in TestRIG.
RVFI-DII extends RVFI with the Direct Instruction Injection input channel.
TestRIG uses RVFI-DII as its standardized communication interface.
Toooba is instrumented with RVFI-DII using superscalar fetch and ID assignment.
Piccolo is instrumented with RVFI-DII for use in TestRIG.
Flute is instrumented with RVFI-DII for use in TestRIG.
Flute is instrumented with RVFI-DII using a DII queue replacing the instruction cache.
RVBS is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
Piccolo is instrumented with RVFI-DII, with the cache replaced by a DII queue.
RVFI-DII defines the DII Stream format for instruction traces.
Ibex is instrumented with RVFI-DII for use in TestRIG.
RVBS is a RISC-V reference implementation instrumented with RVFI-DII.
The Sail model implements the RVFI-DII interface.
QCVEngine communicates with implementations via RVFI-DII sockets.
Direct Instruction Injection is the DII component of the RVFI-DII interface.
Ibex is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
RVFI-DII defines the RVFI Stream format for execution traces.
RVFI-DII is implemented and used in the TestRIG infrastructure for processor verification.
DII (Direct Instruction Injection) is a component of the RVFI-DII interface.
Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.
QEMU was extended with the Direct Instruction Injection interface to support TestRIG verification.
Direct Instruction Injection is the input component of the RVFI-DII interface.
The BSV-RVFI-DII library provides a Bluespec implementation of the RVFI-DII interface.
Flute has been instrumented with RVFI-DII.
Piccolo has been instrumented with RVFI-DII.
RVFI-DII is an extension of the RISC-V Formal Interface standard.
RVFI-DII extends RVFI by adding Direct Instruction Injection capabilities.
Spike has been extended with the Direct Instruction Injection interface for use with TestRIG.
QEMU has been extended with the Direct Instruction Injection interface for use with TestRIG.
RVFI-DII combines RVFI trace output with Direct Instruction Injection input.
RVFI-DII uses RVFI as its trace output mechanism.
CHERI-RISC-V VP++ adds RVFI-DII support for TestRIG verification.
QuickCheckVEngine connects to RISC-V implementations via the RVFI-DII interface.
The Direct Instruction Injection interface was added to the Sail RISC-V formal model.
LINKED ENTITIES
1 linksCITATIONS
10 sources10 citations — click to expand
[1] TestRIG is a framework for RISC-V processor verification using the RVFI-DII (pronounced "rividy") interface. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[2] Vengines generate one or more DII streams of instruction traces and consume one or more RVFI streams of execution traces; implementations consume a DII instruction trace and generate an RVFI execution trace. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[3] The vengine feeds itraces into both a model and an implementation through two TCP sockets in the RVFI-DII format, the model and implementation return an RVFI-DII etrace detailing the state observation and state change of each instruction, and the vengine compares these two traces to identify any divergence. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[4] Implementations consume instructions exclusively from the RVFI-DII instruction port, bypassing any actual instruction memory and ignoring the architectural program counter, and deliver a trace report at the end of execution in the RVFI-DII format. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[5] The RVFI-DII communication uses a single socket with the itrace consumed and the etrace delivered over the same socket. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[6] TestRIG eliminates the "test gap" between specification and implementation by using an executable model as the specification, allowing automated verification of any specified property without passing through human interpretation and hand-writing tests. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[7] TestRIG verifies the pipeline as well as specification compliance: under random sequence generation every register value read in the pipeline can be observed, whereas a test suite only reports a prescribed test result. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[8] Because DII bypasses fetch through the PC, a sequence of instructions can easily be shortened by eliminating instructions from the trace to see if divergence still occurs, yielding automatically reduced counterexamples on the order of a handful of instructions. GitHub - CTSRD-CHERI/TestRIG: Testing processors with Random Instruction Generation · GitHub
[9] TestRIG supports a "single implementation" mode that runs an implementation on its own and asserts more liberal properties over the RVFI trace (for example, instruction count in equals instruction count out to detect processor lockup); DII is required to allow such liberal testing without having to reason about control flow. [PDF] CAMBRIDGE - RISC-V Summit Europe
[10] Single-implementation-mode testing via DII has uncovered cases such as a processor mis-decoding and locking up on certain illegal instructions, a subtle and rare compressed-branch mispredict infinite loop, and a reachable fatal assert condition in a version of the Sail model. [PDF] CAMBRIDGE - RISC-V Summit Europe