RVFI-DII
ConceptRVFI-DII (pronounced "rividy") is the TestRIG-compatible combination of the RISC-V Formal Interface (RVFI) for per-instruction state observation and Direct Instruction Injection (DII) for harness-driven instruction supply, used by vengines and implementations to compare RISC-V models, simulators, and simulated hardware through generated instruction streams and trace comparison over a single socket.
First seen 5/27/2026
Last seen 7/19/2026
Evidence 21 chunks
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WIKI
Overview
RVFI-DII (pronounced "rividy") is the combined verification interface used by the TestRIG framework. It joins the RISC-V Formal Interface (RVFI), a tracing protocol for RISC-V processors to specify the results of running instructions, with Direct Instruction Injection (DII), in which the next instruction is supplied by the test harness rather than fetched from program memory. TestRIG describes itself as "a framework for RISC-V processor verification using the RVFI-DII interface," and the full wire format is documented in the project repository's RVFI-DII specification.
Components and data flow
NEIGHBORHOOD
8 nodes · 19 edgesgraph · RVFI-DII · depth=1
RELATIONSHIPS
36 connectionsTestRIG uses the RVFI-DII interface for cross-verification.
The paper introduces RVFI-DII as a combined interface for instruction injection and trace output.
Toooba is instrumented with RVFI-DII for use in TestRIG.
RVFI-DII extends RVFI with the Direct Instruction Injection input channel.
TestRIG uses RVFI-DII as its standardized communication interface.
Toooba is instrumented with RVFI-DII using superscalar fetch and ID assignment.
Piccolo is instrumented with RVFI-DII for use in TestRIG.
Flute is instrumented with RVFI-DII for use in TestRIG.
Flute is instrumented with RVFI-DII using a DII queue replacing the instruction cache.
RVBS is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
Piccolo is instrumented with RVFI-DII, with the cache replaced by a DII queue.
RVFI-DII defines the DII Stream format for instruction traces.
Ibex is instrumented with RVFI-DII for use in TestRIG.
RVBS is a RISC-V reference implementation instrumented with RVFI-DII.
The Sail model implements the RVFI-DII interface.
QCVEngine communicates with implementations via RVFI-DII sockets.
Direct Instruction Injection is the DII component of the RVFI-DII interface.
Ibex is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
RVFI-DII defines the RVFI Stream format for execution traces.
RVFI-DII is implemented and used in the TestRIG infrastructure for processor verification.
DII (Direct Instruction Injection) is a component of the RVFI-DII interface.
Spike was extended with the Direct Instruction Injection interface to support TestRIG verification.
QEMU was extended with the Direct Instruction Injection interface to support TestRIG verification.
Direct Instruction Injection is the input component of the RVFI-DII interface.
The BSV-RVFI-DII library provides a Bluespec implementation of the RVFI-DII interface.
Flute has been instrumented with RVFI-DII.
Piccolo has been instrumented with RVFI-DII.
RVFI-DII is an extension of the RISC-V Formal Interface standard.
RVFI-DII extends RVFI by adding Direct Instruction Injection capabilities.
Spike has been extended with the Direct Instruction Injection interface for use with TestRIG.
QEMU has been extended with the Direct Instruction Injection interface for use with TestRIG.
RVFI-DII combines RVFI trace output with Direct Instruction Injection input.
RVFI-DII uses RVFI as its trace output mechanism.
CHERI-RISC-V VP++ adds RVFI-DII support for TestRIG verification.
QuickCheckVEngine connects to RISC-V implementations via the RVFI-DII interface.
The Direct Instruction Injection interface was added to the Sail RISC-V formal model.
CITATIONS
7 sources7 citations — click to expand
[1] RVFI-DII is pronounced "rividy" and is the interface TestRIG uses for RISC-V processor verification. CTSRD-CHERI/TestRIG
[2] TestRIG supports two component types: vengines that generate DII streams and consume RVFI streams, and implementations that consume DII traces and produce RVFI traces. CTSRD-CHERI/TestRIG
[3] A vengine feeds itraces into both a model and an implementation through two TCP sockets in the RVFI-DII format and returns RVFI-DII etraces detailing state observation and change for each instruction. CTSRD-CHERI/TestRIG
[4] Implementations consuming RVFI-DII consume instructions exclusively from the RVFI-DII instruction port, bypassing actual instruction memory and ignoring the architectural program counter, then deliver a trace report in the RVFI-DII format. CTSRD-CHERI/TestRIG
[5] The RVFI-DII communication uses a single socket with the itrace consumed and the etrace delivered over the same socket. CTSRD-CHERI/TestRIG
[6] RISC-V Formal Interface (RVFI) is a tracing protocol for RISC-V processors to specify results of running instructions, and RVFI-DII is defined as the use of Direct Instruction Injection (DII) and RVFI together. UCAM-CL-TR-984.pdf
[7] TestRIG positions RVFI-DII as eliminating the test gap between specification and implementation, enabling pipeline-level verification, and producing small automatically reduced counterexamples. CTSRD-CHERI/TestRIG