UCAM-CL-TR-984
PaperFirst seen 6/8/2026
Last seen 6/8/2026
Evidence 17 chunks
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50 connectionsDirect Instruction Injection (DII) is used as a protocol for testing RISC-V processors via TestRIG.
Instruction Set Architecture (ISA) is discussed in the context of CHERI's implementation on RISC-V.
The thesis evaluates the CHERI-extended Piccolo microcontroller including area, frequency, performance, and power overheads.
The thesis evaluates the CHERI-extended Flute microcontroller including area, frequency, performance, and power overheads.
The thesis evaluates the CHERI-extended Toooba superscalar processor.
TestRIG is used for correctness validation of the CHERI processor implementations.
QuickCheckVEngine is used as the verification engine within TestRIG for testing the CHERI processor implementations.
RVFI-DII is implemented and used in the TestRIG infrastructure for processor verification.
The thesis uses FPGA prototyping to evaluate the CHERI processor implementations.
The thesis investigates temporal safety techniques using CHERI for RISC-V processors.
The thesis investigates and optimises sweeping revocation for temporal safety with CHERI.
The thesis includes work on safe speculation for CHERI processors, including a co-authored paper on architectural contracts for safe speculation.
The thesis implements and evaluates the merged register file for CHERI microcontrollers.
The thesis implements and evaluates the capability mode bit for CHERI microcontrollers.
Program Counter Capability is implemented as part of the CHERI extensions to the processors.
The tag controller AXI component is used and improved for the RISC-V CHERI implementations.
Bluespec HDL is used as the hardware description language for implementing the CHERI processors.
Physical Memory Protection (PMP) is discussed in the context of memory safety and compared to capabilities.
Memory Management Units are discussed in the context of memory protection and spatial safety.
Memory Protection Units are discussed in the context of microcontroller memory safety.
MIPS is discussed as the initial architecture on which CHERI was implemented.
Morello is mentioned as Arm's concurrent CHERI implementation research prototype.
RISC-V Formal Interface (RVFI) is used as a tracing protocol for verification.
The thesis implements the Sentry mechanism as part of the CHERI Toooba implementation.
The thesis contributes to CHERIvoke research including developing the sweeping algorithm and shadow-bitmap idea.
The shadow bitmap idea is contributed by the author as part of CHERIvoke work.
CHERI-Concentrate capability compression is used in the Morello prototype and referenced in this work.
Virtual memory is discussed as part of the sweeping revocation optimisation strategy.
Linear capabilities are discussed as an alternative capability semantics for temporal safety.
Indirect capabilities are discussed as an alternative capability semantics for temporal safety.
The thesis acknowledges DARPA funding support.
The thesis investigates the implementation of CHERI secure capabilities for RISC-V microarchitectures.
The thesis implements CHERI on RISC-V microarchitectures.
Return-Oriented Programming is mentioned as an attack technique in the security background.
Capability hardware security is the central security concept of the thesis.
The CHERI Capability Library is developed and used for capability format operations.
The thesis evaluates RiscyOO as the first open superscalar CHERI implementation.
The Sail CHERI-RISC-V model is used and contributed to as a reference model.
BlueStuff Bluespec libraries are used and improved for the memory subsystems of the CHERI implementations.
The technical report was authored by Peter David Rugg as his PhD dissertation.
MiBench benchmarks are used to evaluate performance of the CHERI processor implementations.
CoreMark benchmarks are used to evaluate performance of the CHERI processor implementations.
SPEC benchmarks are used to evaluate performance of the CHERI Toooba processor.
Vivado is used for FPGA synthesis and power reporting of the CHERI processors.
The technical report was published by the University of Cambridge Computer Laboratory.
RISC-V BOOM is mentioned as another superscalar RISC-V core alongside RiscyOO.
The thesis investigates spatial memory safety via CHERI implementations.
The thesis develops the first open CHERI implementation for a superscalar out-of-order processor.
The thesis implements CHERI for microcontrollers as one of its key contributions.
The thesis implements and modifies instruction pipelines for the CHERI processors.