Paper
Paper
86 entities#
1 Verifying Instruction Set Simulators using Coverage-guided Fuzzing
27 2 Code Generation for Custom Architectures using Constraint Programming
19 3 Randomized Testing of RISC-V CPUs using Direct Instruction Injection
17 4 UCAM-CL-TR-984
17 5 Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
17 6 Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
15 7 DiffTest-H
15 8 Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
15 9 Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
15 10 RVDFI
15 11 Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms
14 12 Test Program Generation for a Microprocessor: A Case-Study
13 13 Generating an Efficient Instruction Set Simulator from a Complete Property Suite
13 14 Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging
12 15 Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
12 16 UVM Based Design Verification of a RISC-V CPU Core
12 17 Code-based Test Generation for Validation of Functional Processor Descriptions
11 18 MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
11 19 Testing CPU Emulators
11 20 UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach
10 21 Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
10 22 Functional Verification of a RISC-V Vector Accelerator
10 23 Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
9 24 Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method
9 25 rtlv: push-button verification of software on hardware
9 26 Code Generation and Analysis for the Functional Verification of Microprocessors
8 27 Advanced Automation in Formal Verification of Processors
8 28 Towards Verified Faithful Simulation
7 29 Bryant-O'Hallaron Computer Systems Textbook
6 30 Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
5 31 Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM
5 32 ProcessorFuzz paper
5 33 Automation of Processor Verification Using Recurrent Neural Networks
5 34 INSTILLER: Towards Efficient and Realistic RTL Fuzzing
4 35 TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
4 36 Constraint-based Random Stimuli Generation for Hardware Verification
4 37 Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts
4 38 Instiller paper
3 39 PIM-DFI
3 40 ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers
3 41 A Test Generation Framework for Datapath Floating-Point Verification
3 42 Adaptive Test Program Generation: Planning for the Unplanned
3 43 Using Constraint Satisfaction Formulations and Solution Techniques for Random Test Program Generation
3 44 Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
3 45 HDFI
3 46 ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
2 47 Generating Instruction Streams Using Abstract CSP
2 48 Industrial Experience with Test Generation Languages for Processor Verification
2 49 Functional Verification of the POWER5 Microprocessor and POWER5 Multiprocessor Systems
2 50 Test Program Generation for Functional Verification of PowerPC Processors in IBM
2 51 Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation
2 52 Fuzzing Hardware Like Software
2 53 RFUZZ: Coverage-directed fuzz testing of RTL on FPGAs
2 54 Extensible and configurable RISC-V based virtual prototype
2 55 DeepTrans - A Model-Based Approach to Functional Verification of Address Translation Mechanisms
2 56 X-Gen: A Random Test-Case Generator for Systems and SoCs
2 57 TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
2 58 Handcrafted Inversions Made Operational on Operational Semantics
2 59 seL4: Formal Verification of an OS Kernel
2 60 Model Based Test Generation for Processor Verification
2 61 Benchmarking Large Language Models for Automated Verilog RTL Code Generation
2 62 RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
2 63 StarCoder 2 and The Stack v2: The Next Generation
2 64 Advanced Verification Suite for RISC-V Cores
2 65 Addressing Verification Challenges of Heterogeneous Systems Based on IBM Power9
2 66 Crafting a Million Instructions/Sec RISCV-DV
2 67 TMDFI
2 68 Assumption-based Pruning in Conditional CSP
2 69 Who tests the TestRIG? Tooling for randomised tandem verification
1 70 MicroTESK: specification-based tool for constructing test program generators
1 71 Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools
1 72 Closing the RISC-V compliance gap: Looking from the negative testing side
1 73 Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
1 74 What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications
1 75 Hybrid Intelligent Testing in Simulation-Based Verification
1 76 Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic
1 77 Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
1 78 Optimizing Design Verification using Machine Learning: Doing better than Random
1 79 Generation of a QEMU-Based Instruction Set Simulator from a Processor Description in OpenVADL
1 80 Reversi: Post-silicon validation system for modern microprocessors
1 81 PATARA: A REVERSI-based open-source tool for post-silicon validation of processor cores
1 82 Directing greybox fuzzing to discover bugs in hardware and software
1 83 Proceedings Article 2025-10-26
1 84 Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
1 85 ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
1 86 Towards specification and testing of RISC-V ISA compliance
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