Paper
Paper
280 entities#
1 Verifying Instruction Set Simulators using Coverage-guided Fuzzing
29 2 Processor Verification using Symbolic Execution: A RISC-V Case-Study
27 3 Code Generation for Custom Architectures using Constraint Programming
19 4 Cascade: CPU fuzzing via intricate program generation
18 5 Randomized Testing of RISC-V CPUs using Direct Instruction Injection
18 6 Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
17 7 UCAM-CL-TR-984
17 8 Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation
16 9 RVDFI
15 10 Synthesizing Instruction Selection Rewrite Rules from RTL using SMT
15 11 DiffTest-H
15 12 μCFI: Formal Verification of Microarchitectural Control-flow Integrity
15 13 Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
15 14 Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
14 15 Towards Reliable and Secure RISC-V Systems: Survey of Testability and Security Mechanisms
14 16 Hardware accelerated constrained random test generation
14 17 Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
14 18 Coverage-driven Functional Test Generation for Processor Validation using Formal Methods
14 19 Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging
13 20 Generating Test Programs to Cover Pipeline Interactions
13 21 A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
13 22 Fine-Grained Code Analysis for Processor Fuzzing
13 23 A Framework for Guided Test Case Generation in Constraint Logic Programming
13 24 Generating an Efficient Instruction Set Simulator from a Complete Property Suite
13 25 Test Program Generation for a Microprocessor: A Case-Study
13 26 Test-Driven Generation of CSPs Using LLMs
12 27 Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
12 28 UVM Based Design Verification of a RISC-V CPU Core
12 29 Generating Instruction Streams Using Abstract CSP
12 30 Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
12 31 An Approach to Test Programs Generation for Microprocessors Based on Pipeline Hazards Templates
12 32 Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
12 33 MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
11 34 Code-based Test Generation for Validation of Functional Processor Descriptions
11 35 Contradiction Analysis for Constraint-based Random Simulation
11 36 Mutation-based Compliance Testing for RISC-V
11 37 Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
11 38 An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
11 39 Testing CPU Emulators
11 40 Functional Verification of a RISC-V Vector Accelerator
10 41 AI based SystemVerilog TB generation
10 42 A Methodology for Validation of Microprocessors using Equivalence Checking
10 43 Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
10 44 Towards a framework for constraint-based test case generation
10 45 UVM-based verification of RISC-V superscalar processors: A reinforcement learning approach
10 46 Performance of a SystemVerilog Sudoku Solver with VCS
10 47 Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models
10 48 FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
10 49 Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators
9 50 rtlv: push-button verification of software on hardware
9 51 Single instruction isolation for RISC-V vector test failures
9 52 Reusable Verification Environment for a RISC-V Vector Accelerator
9 53 Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review
9 54 UniGen Paper (DAC 2014)
9 55 Large-Scale RISC-V Processor Verification Using Automated Design Inspection and a Generic Simulation Method
9 56 Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures
9 57 DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification
9 58 Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
8 59 LLM4DV
8 60 Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
8 61 Code Generation and Analysis for the Functional Verification of Microprocessors
8 62 Hardware Support to Improve Fuzzing Performance and Precision
8 63 Advanced Automation in Formal Verification of Processors
8 64 μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections
7 65 Towards Verified Faithful Simulation
7 66 ProcessorFuzz paper
7 67 Automation of Processor Verification Using Recurrent Neural Networks
7 68 TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing
7 69 A Comparison of Three Verification Techniques: Directed Testing, Pseudo-Random Testing and Property Checking
7 70 HARTBREAKER paper
7 71 Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
7 72 Improvements for Constraint Solving in the SystemC Verification Library
6 73 Bryant-O'Hallaron Computer Systems Textbook
6 74 An Advanced Constrained Random Verification Environment for SystemC
6 75 COMS30026 Design Verification: Stimuli Generation
6 76 Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing
6 77 Understanding UVM Coverage for RISC-V Processor Designs
6 78 Guiding Greybox Fuzzing with Mutation Testing
6 79 EPEX: Processor Verification by Equivalent Program Execution
6 80 Synthesizing Programs with Continuous Optimization
5 81 GenHuzz: An Efficient Generative Hardware Fuzzer
5 82 ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance
5 83 RFuzz Paper
5 84 Constraint-based Random Stimuli Generation for Hardware Verification
5 85 Bug hunting SoC designs to achieve full functional coverage closure
5 86 GoldenFuzz: Generative Golden Reference Hardware Fuzzing
5 87 A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture
5 88 MicroTESK: An Extendable Framework for Test Program Generation
5 89 Towards specification and testing of RISC-V ISA compliance
5 90 Multi-target Coverage-based Greybox Fuzzing (Master's Thesis 2025)
5 91 Examiner: Automatically Locating Inconsistent Instructions between Real Devices and CPU Emulators for ARM
5 92 Genesys: Automatically Generating Representative Training Sets for Predictive Benchmarking
5 93 Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator
5 94 ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers
5 95 CRAVE: An Advanced Constrained Random Verification Environment for SystemC
4 96 Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V
4 97 DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
4 98 RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis
4 99 INSTILLER: Towards Efficient and Realistic RTL Fuzzing
4 100 TIUP: Effective Processor Verification with Tautology-Induced Universal Properties
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