Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models

Paper

First seen 6/6/2026

Last seen 6/6/2026

Evidence 10 chunks

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RELATIONSHIPS

24 connections

Verilator uses → 97% 2e

The paper uses Verilator to generate RTL-based execution models

Tandem Generator uses → 95% 2e

The paper uses the Tandem Generator tool to automate tandem simulation

Simulation-Based Testing uses → 95% 2e

The paper is based on simulation-based testing methodology

Transaction-Level Model (TLM) mentions → 90% 2e

The paper discusses TLM/RTL co-simulation as related work

Tandem Simulation introduces → 95% 2e

The paper generalizes and introduces an automated tandem simulation methodology for both processors and accelerators

Refinement Map uses → 97% 2e

The paper uses refinement maps to automate tandem simulation

AES-RTL (Block Implementation) evaluates → 95% 2e

The paper evaluates AES block implementation as a case study

AES ILA Model evaluates → 92% 2e

The paper evaluates the AES ILA model in case studies

AES-RTL (Round Implementation) evaluates → 95% 2e

The paper evaluates AES round implementation as a case study

FlexNLP RTL evaluates → 93% 2e

The paper evaluates FlexNLP RTL as a case study

PicoRV32 (Pico) evaluates → 93% 2e

The paper evaluates PicoRV32 as a case study

Piccolo RISC-V Core evaluates → 93% 2e

The paper evaluates Piccolo RISC-V core as a case study

Rocket Core evaluates → 93% 2e

The paper evaluates Rocket Core as a case study

ILAtor uses → 97% 2e

The paper uses ILAtor to automatically generate ILEMs

ILAng uses → 97% 2e

The paper uses ILAng for ILA modeling

DARPA ← part of 85% 1e

DARPA co-sponsored the research through the ADA Research Center

Aarti Gupta authored by → 100% 1e

The paper is authored by Aarti Gupta

Sharad Malik authored by → 100% 1e

The paper is authored by Sharad Malik

Princeton University published by → 100% 1e

The paper is from Princeton University

Instruction-Level Abstraction (ILA) uses → 98% 1e

The paper leverages ILA to extend tandem simulation to accelerators

System-on-Chip (SoC) mentions → 90% 1e

The paper discusses SoCs in the context of applying tandem simulation

Random Test Input Generation uses → 93% 1e

The paper uses randomly generated test inputs for evaluation

RISC-V ILA Model evaluates → 90% 1e

The paper evaluates RISC-V ILA model in processor case studies

Yue Xing authored by → 100% 1e

The paper is authored by Yue Xing