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STIMSMITH

Instruction-Level Abstraction (ILA)

Concept
First seen 6/6/2026
Last seen 6/6/2026
Evidence 8 chunks

NEIGHBORHOOD

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RELATIONSHIPS

13 connections
ILAng ← implements 97% 2e
ILAng is the platform for ILA modeling
Instruction Set Architecture (ISA) extends → 97% 2e
ILA generalizes the ISA for accelerators as well as processors
Decode Function ← part of 95% 1e
ILA includes decode functions as part of its instruction definition
State Update Function ← part of 95% 1e
ILA includes state update functions as part of its instruction definition
Architectural Variable (AV) ← part of 97% 1e
ILA specifies a set of architectural variables
Child-ILA (Child Instructions) ← part of 95% 1e
ILA supports child-ILAs for complex instructions
Memory-Mapped Input/Output (MMIO) uses → 92% 1e
ILA models MMIO-controlled accelerators by treating loads/stores as instructions
ILAtor ← uses 98% 1e
ILAtor takes an ILA model as input
AES ILA Model ← implements 97% 1e
AES ILA Model is an ILA model for the AES accelerator
RISC-V ILA Model ← implements 95% 1e
RISC-V ILA model is an ILA specification of the RISC-V ISA
Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models ← uses 98% 1e
The paper leverages ILA to extend tandem simulation to accelerators
Instruction-Level Execution Model (ILEM) ← derived from 97% 1e
ILEM is automatically generated from the ILA model
Tandem Simulation ← uses 97% 1e
Tandem simulation leverages ILA for accelerator modeling