Verilator
ToolVerilator is an open-source SystemVerilog simulator and lint system. In the provided processor-verification evidence, ProcessorFuzz uses Verilator as the open-source RTL simulator for RTL simulation of all evaluated processor designs, producing RTL trace logs for comparison against ISA-simulator traces.
First seen 5/26/2026
Last seen 6/9/2026
Evidence 14 chunks
Wiki v4
WIKI
Verilator
Overview
Verilator is an open-source SystemVerilog simulator and lint system. Its public GitHub repository is verilator/verilator. [citation: Verilator is an open-source SystemVerilog simulator and lint system]
NEIGHBORHOOD
3 nodes · 3 edgesgraph · Verilator · depth=1
RELATIONSHIPS
12 connectionsProcessorFuzz uses Verilator for RTL simulation of processor designs.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 4e
The paper references Verilator used in the experimental setup.
The paper uses Verilator to obtain a C++ description of the RTL core.
The paper uses Verilator to translate the RTL-core to C++ for co-simulation.
DiffTest-H is compared against 16-thread Verilator for simulation speed.
The paper uses Verilator to generate RTL-based execution models
Verilator is used for RTL simulation in ProcessorFuzz.
Verilator is an RTL simulator.
DIFUZZRTL uses Verilator as an RTL simulator for software simulation.
Verilator generates the RTEM from Verilog RTL
Verilator is an open-source tool implementing RTL simulation.
Verilator is used to compile the RTL-core into C++ for integration into the co-simulation.
LINKED ENTITIES
2 linksCITATIONS
6 sources6 citations — click to expand
[2] ProcessorFuzz uses Verilator for RTL simulation ProcessorFuzz: Processor Fuzzing with Control and
[3] ProcessorFuzz RTL simulation and trace comparison ProcessorFuzz: Processor Fuzzing with Control and
[4] ProcessorFuzz uses Spike for ISA traces and Verilator for RTL simulation ProcessorFuzz: Processor Fuzzing with Control and