Verilator
ToolVerilator is an open-source SystemVerilog simulator and lint system. It compiles Verilog/SystemVerilog designs into optimized, potentially multithreaded C++/SystemC models that run faster than interpreted simulation. Verilator is used as the RTL simulation backend in several hardware-fuzzing and verification frameworks (including ProcessorFuzz, RFuzz, DirectFuzz, and FuSS), and is the basis for ongoing work on UVM testbench support via the uvm-verilator project.
First seen 5/26/2026
Last seen 9/16/2026
Evidence 86 chunks
Wiki v5
WIKI
Verilator
Overview
Verilator is an open-source SystemVerilog simulator and lint system. Its public GitHub repository is verilator/verilator. [citation: Verilator is an open-source SystemVerilog simulator and lint system]
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
50 connectionsChiGen was used in bug-finding campaigns on Verilator, revealing crashes and issues.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 90% 4e
The paper references Verilator used in the experimental setup.
ProcessorFuzz uses Verilator for RTL simulation of processor designs.
The paper uses Verilator to translate the Verilog RTL processor into C++ for co-simulation.
Antmicro is actively developing UVM integrations with Verilator
Verilator translates SystemVerilog RTL into C++ models.
Antmicro is working on enabling fully open source UVM support in Verilator.
The paper uses Verilator to translate the RTL core to C++ for co-simulation.
DeepVerifier uses Verilator as an RTL simulator to capture coverage scores.
Verilator is an open-source RTL simulator that converts hardware designs to C++ functional models
The paper uses Verilator to obtain a C++ description of the RTL core.
DiffTest-H is compared against 16-thread Verilator for simulation speed.
The paper uses Verilator to generate RTL-based execution models
The article reports upstream UVM 2017 support in Verilator, indicating implementation of UVM features.
RISCSmith uses Verilator to compile and simulate instrumented RISC-V implementations.
Cascade uses Verilator to simulate CPUs' RTL.
StimulusRL can be integrated into Verilator-based simulation flows.
Prelude is compared against Verilator as a software simulation baseline.
Verilator is an RTL simulation tool providing full signal visibility.
Rapid Fault Injection Simulation by Hash-based Differential Fault Effect Equivalence Checks ← uses 100% 1e
The paper uses Verilator as the RTL simulation basis.
Verilator is used to compile the SpinalHDL RTL PLIC to SystemC RTL.
vRTLmod transforms Verilator's output (vRTL) to enable fault injection.
Verilator compiles the SpinalHDL-generated RTL PLIC to SystemC RTL for simulation.
vRTL is the C++ output produced by Verilator from Verilog RTL.
Verilator generates the RTEM from Verilog RTL
Ara can be simulated using Verilator, which is used in this work.
The paper uses Verilator as the simulation backend.
Verilator is used to translate RTL designs into C++.
RFuzz uses Verilator to simulate the DUT in its simulation-based approach.
DirectFuzz uses Verilator for hardware simulation, like RFuzz.
FuSS uses Verilator to convert hardware models into cycle-accurate software models.
Verilator implements cycle-accurate simulation of hardware designs.
HARTBREAKER uses Verilator to simulate designs under test.
Verilator is used as a single-threaded RTL simulator
The LLM4DV framework uses Verilator for simulation and testing of DUT modules.
Verilator supports line, toggle and functional coverage analysis.
The Docker image for UnityChipForXiangShan includes Verilator as a tool.
The Docker image includes Verilator as a bundled tool.
Verilator now implements constrained randomization as introduced by Antmicro.
Toooba depends on Verilator as part of its build requirements.
Verilator uses SMT solvers in the implementation of randomization constraints.
Verilator uses z3 as an SMT solver for implementing randomization constraints.
Verilator uses cvc5 as an SMT solver for implementing randomization constraints.
Verilator converts SystemVerilog expressions to SMT-LIB2 as part of its constraint solving integration.
Ibex depends on Verilator for its build process within TestRIG.
HiFuzz is implemented on top of Verilator for RTL simulation.
ZP Cosim supports simulation using Verilator as a backend
XiangShan supports Verilator as a simulation backend.
googletest-hdl was extended to support Verilator as a simulation backend.
The RISC-V soft-core contest required the use of Verilator as a simulator for the FWRISC core.
CITATIONS
11 sources11 citations — click to expand
[1] Verilator is an open-source SystemVerilog simulator and lint system, with public repository verilator/verilator. verilator/verilator
[2] Verilator compiles Verilog or SystemVerilog code into an optimized, potentially multithreaded model wrapped in a C++/SystemC module, executing faster than interpreted simulators and on par with or better than many closed-source simulators. Fuzzing IPv4 modules on FPGAs
[3] ProcessorFuzz uses Verilator as the open-source RTL simulator for all evaluated processor designs, comparing RTL trace logs against ISA trace logs. Fuzzing IPv4 modules on FPGAs
[4] RFuzz uses Verilator to simulate the DUT on the CPU side of an SoC, communicating with the fuzzer via shared-memory buffers. Fuzzing IPv4 modules on FPGAs
[5] DirectFuzz builds on RFuzz and likewise uses Verilator for hardware simulation. Fuzzing IPv4 modules on FPGAs
[6] FuSS uses Verilator to convert hardware models into cycle-accurate software models; Verilator serves as the backend due to precise modeling of synthesizable Verilog designs. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[7] The Cascade artifact uses Verilator v5.006 and provides an explicit reinstall procedure if the running Verilator version produces an unknown-warning error. comsec-group/cascade-artifacts
[8] Long-running efforts led by Antmicro, Wilson Snyder, and open-source contributors enable UVM testbenches in Verilator via the uvm-verilator project, with upstream UVM 2017 support as a milestone. CHIPS Alliance SV Tools Project launch
[9] The CHIPS Alliance sv-tests suite tracks Verilator's SystemVerilog feature support and was used to track milestones such as the addition of UVM support to Verilator. CHIPS Alliance SV Tools Project launch
[10] Verilator is discussed in a survey of RISC-V processor verification alongside RVVI-Trace, RVVI-VVP, and RISCV-DV as part of the open-source verification ecosystem. Survey of Verification of RISC-V Processors
[11] A DATE 2022 cross-level processor-verification excerpt references https://www.veripool.org/verilator/ but does not provide enough surrounding detail to support stronger claims about its role in that work. Verilator project page