Co-Simulation

Technique

In the supplied processor-verification evidence, co-simulation is used to compare an RTL RISC-V processor against a reference instruction-set simulator in a shared SystemC testbench. The documented case study combines co-simulation with coverage-guided fuzzing for the VexRiscv RV32IM configuration, using Verilator to translate the RTL core to C++ and an ISS extracted from the RISC-V VP as the reference model.

First seen 5/25/2026

Last seen 6/2/2026

Evidence 20 chunks

Wiki v4

WIKI

Overview

In the supplied evidence, co-simulation is a processor-verification technique in which an RTL processor core and a reference instruction-set simulator (ISS) are embedded into a common testbench so their behavior can be checked during generated test execution. The documented case study evaluates fuzzing in combination with co-simulation for processor verification. [C1]

Coverage-guided fuzzing case study

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NEIGHBORHOOD

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RELATIONSHIPS

17 connections

Functional Verification of a RISC-V Vector Accelerator ← uses 99% 4e

The verification performs step-by-step co-simulation of all vector instructions

Cross-Level Testing ← uses 100% 4e

Cross-level testing employs co-simulation between ISS and RTL core.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 4e

The paper uses a co-simulation setting with an ISS as reference model for the RTL processor.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses co-simulation between ISS and RTL core for verification.

co-simulation testbench ← implements 100% 2e

The co-simulation testbench implements the co-simulation technique.

Co-Simulation Testbench uses → 90% 2e

Co-simulation is realized via the co-simulation testbench that connects ISS and RTL core.

spike uses → 99% 2e

Spike is used as the reference ISA simulator for co-simulation

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 2e

The paper leverages co-simulation with ISS as a reference model

Reference Model uses → 97% 2e

Co-simulation relies on a reference model to compare results

Translation Buffer uses → 95% 2e

The co-simulation uses the Translation Buffer to convert bounded test vectors into endless instruction streams.

Execution Controller uses → 95% 2e

The co-simulation uses the Execution Controller to prevent infinite loops and detect mismatches.

Cross-Level Processor Verification ← uses 100% 1e

Cross-level processor verification uses co-simulation with ISS

Execution Controller ← part of 100% 1e

The Execution Controller is part of the co-simulation framework.

The co-simulation uses register value comparison to detect functional mismatches.

Verilator uses → 95% 1e

Verilator is used to compile the RTL-core into C++ for integration into the co-simulation.

RISC-V Design Verification (DV) Framework ← uses 90% 1e

The RISC-V DV framework employs co-simulation with an ISS

Translation Buffer ← part of 100% 1e

The Translation Buffer is a component of the co-simulation framework.

LINKED ENTITIES

4 links

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study USES Extracted graph relationship

co-simulation testbench IMPLEMENTS Extracted graph relationship

Cross-Level Testing USES Extracted graph relationship

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing USED_BY The paper explicitly evaluates fuzzing in combination with co-simulation for processor verification and describes the VexRiscv/SystemC/ISS co-simulation setup.

CITATIONS

4 sources

4 citations — click to collapse

[1] The fuzzing case study evaluates co-simulation for processor verification using VexRiscv as the RTL DUT, a RISC-V VP ISS as reference, Verilator translation to C++, and a common SystemC testbench. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] The fuzzing flow adds CSR write/read instruction pairs so CSR misbehavior is propagated into a register and made detectable by the Execution Controller. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] The post-processing flow uses a custom co-simulation that logs executed instructions and addresses, is slower due to hard-disk writes, does not require fuzzing coverage instrumentation, and is used to extract the instruction leading to a bug. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] The fuzzing paper contrasts its approach with earlier cross-level testing work, identified in the references as 'Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study,' noting that the earlier setup required significant manual effort for co-simulation across processor configurations. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing