Co-Simulation

Technique

In the supplied evidence, co-simulation is a verification technique in which an RTL processor core and a reference instruction-set simulator (ISS) are run in lock-step so their behavior can be compared during instruction-level testing. The documented case studies combine co-simulation with coverage-guided fuzzing for the VexRiscv RV32IM configuration and with random/directed instruction generation in the RISCV-DV framework, which executes generated programs on the core under test and a reference ISS (such as Spike) and compares register writebacks after each instruction.

First seen 5/25/2026

Last seen 7/11/2026

Evidence 27 chunks

Wiki v5

WIKI

Overview

In the supplied evidence, co-simulation is a processor-verification technique in which an RTL processor core and a reference instruction-set simulator (ISS) are run together on the same generated program so that their behavior can be checked during execution. The same general idea — coupling two simulators and comparing their state — is also used outside the processor domain to study cyber-physical systems, for example coupling a power-system simulator with a communication-network simulator. [C1][C2]

In the processor-verification setting, two concrete instances of this technique are documented in the evidence:

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NEIGHBORHOOD

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RELATIONSHIPS

24 connections

Cross-Level Testing ← uses 100% 5e

Cross-level testing uses co-simulation of both RTL core and reference ISS.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← uses 100% 4e

The paper uses a co-simulation setting with an ISS as reference model for the RTL processor.

Functional Verification of a RISC-V Vector Accelerator ← uses 99% 4e

The verification performs step-by-step co-simulation of all vector instructions

co-simulation testbench ← implements 100% 2e

The co-simulation testbench implements the co-simulation technique.

Reference Model uses → 97% 2e

Co-simulation relies on a reference model to compare results

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation ← uses 97% 2e

The paper proposes logic fuzzer enhanced co-simulation for processor verification.

spike uses → 99% 2e

Spike is used as the reference ISA simulator for co-simulation

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 2e

The paper leverages co-simulation with ISS as a reference model

Translation Buffer uses → 95% 2e

The co-simulation uses the Translation Buffer to convert bounded test vectors into endless instruction streams.

Co-Simulation Testbench uses → 90% 2e

Co-simulation is realized via the co-simulation testbench that connects ISS and RTL core.

Execution Controller uses → 95% 2e

The co-simulation uses the Execution Controller to prevent infinite loops and detect mismatches.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses co-simulation between ISS and RTL core for verification.

Difftest ← implements 98% 1e

Difftest implements a co-simulation approach where the DUT runs in lockstep with a golden reference model.

Execution Controller ← part of 100% 1e

The Execution Controller is part of the co-simulation framework.

The co-simulation uses register value comparison to detect functional mismatches.

Verilator uses → 95% 1e

Verilator is used to compile the RTL-core into C++ for integration into the co-simulation.

RISC-V Design Verification (DV) Framework ← uses 90% 1e

The RISC-V DV framework employs co-simulation with an ISS

Cross-Level Processor Verification ← uses 100% 1e

Cross-level processor verification uses co-simulation with ISS

Direct Programming Interface uses → 93% 1e

Co-simulation uses DPI calls to synchronize the implementations.

Reorder Buffer Monitoring uses → 88% 1e

Co-simulation uses reorder buffer monitoring to detect instruction completion.

riscv-dv ← uses 80% 1e

RISCV-DV runs the DUT and a reference ISS concurrently and compares results, which is a co-simulation approach.

ISS uses → 75% 1e

In the described co-simulation flow, the DUT runs in parallel with a reference ISS to compare architectural state.

RTL evaluates → 91% 1e

Co-simulation tests both the RTL core and the reference ISS together.

Translation Buffer ← part of 100% 1e

The Translation Buffer is a component of the co-simulation framework.

LINKED ENTITIES

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riscv-dv USES Extracted graph relationship

ISS USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] The fuzzing case study uses the open-source RISC-V VexRiscv processor as the device under test, configured as RV32IM, and translates the RTL core to C++ with Verilator before embedding it with an ISS extracted from the RISC-V VP into a common SystemC testbench for co-simulation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] The Springer survey figure caption explicitly states that the cross-level testing approach used both the RTL core and the reference ISS in a co-simulation setting. Survey of Verification of RISC-V Processors - Springer Nature

[3] The fuzzing flow inserts CSR instruction pairs (write then read) so that possible CSR misbehavior is propagated into a register and detected by the Execution Controller. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] After fuzzing, a custom logging-enabled co-simulation variant is used to cluster failing test vectors and extract the instruction that leads to a bug, without the coverage instrumentation required during fuzzing. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] RISCV-DV compares register writebacks of the core under test against a reference RISC-V ISS such as Spike or Renode after each executed instruction, and explicitly lists support for co-simulation with spike, riscv-ovpsim, whisper, and sail-riscv. SV Tools Project Launch

[6] The RISCV-DV co-simulation setup has been used in the verification workflows of the VeeR EL2 and Ibex cores. SV Tools Project Launch

[7] FMI-based distributed co-simulation on top of UniFMU enables collaborative modeling and simulation while protecting IP, with the connection initiated by the client and models/binaries living on trusted platforms. FMI-Based Distributed Co-Simulation with Enhanced Security and Intellectual Property Safeguards

[8] A co-simulation platform coupling DIgSILENT PowerFactory with OMNeT++ and Matlab-based EMS applications has been used to analyze cyber-security of energy management systems against data attacks. Co-simulation for Cyber Security Analysis: Data Attacks against Energy Management System