Cross-Level Testing
TechniqueCross-level testing is a processor verification technique presented for RISC-V RTL verification in which a SystemC co-simulation testbench runs an RTL core and an Instruction Set Simulator reference model on matching instruction behavior, then compares their execution states after each instruction.
First seen 5/25/2026
Last seen 5/30/2026
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Overview
Cross-level testing is presented as a processor verification approach based on an on-the-fly, endless instruction stream. In the cited RISC-V work, the testbench feeds this stream to both an RTL core under test and an Instruction Set Simulator (ISS) reference model inside a co-simulation setup.
Co-simulation execution model
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5 connectionsThe paper proposes a cross-level testing approach for processor verification.
Cross-level testing employs co-simulation between ISS and RTL core.
Cross-level testing uses an ISS as a reference model.
Cross-level testing relies on on-the-fly instruction stream generation to drive verification.
Cross-level testing builds on simulation-based verification methods.
CITATIONS
6 sources6 citations — click to expand
[1] Cross-level testing is presented as a processor verification approach using on-the-fly endless instruction-stream generation. Efficient Cross-Level Testing for
[2] The co-simulation testbench is implemented in SystemC and connects an RTL core under test with an ISS reference model. Efficient Cross-Level Testing for
[3] The test controller executes one RTL instruction, executes the same instruction on the ISS, compares execution states including registers, and reports mismatches. Efficient Cross-Level Testing for
[4] Instruction fetching is based on the program counter; RTL instruction fetches generate new instructions, and ISS instruction fetches receive the corresponding RTL-fetched instruction through instruction matching. Efficient Cross-Level Testing for
[5] The RTL core has separate instruction and data memory interfaces, and the testbench translates between RTL signals and TLM transactions to provide a unified memory abstraction for RTL and ISS execution. Efficient Cross-Level Testing for
[6] The data memory is lazy: writes store data, reads return existing data or generate random data for previously unseen addresses, and RTL/ISS data memories use the same random seed to behave identically for matching access sequences. Efficient Cross-Level Testing for