Technique
Technique
365 entities#
1 Coverage-Guided Fuzzing
32 2 CSR-transition coverage
24 3 Co-Simulation
20 4 RTL simulation
14 5 differential testing
13 6 Simulation-Based Verification
12 7 register coverage
12 8 ISA simulation
12 9 Tandem Simulation
11 10 Mutation-Based Fuzzing
11 11 Synchronizable Co-simulation
11 12 Runtime Instruction Morphing
11 13 Object-Oriented Stimulus Generation
11 14 Direct Instruction Injection
10 15 Formal Verification
10 16 Constraint Solving
10 17 Differential Fuzzing
10 18 Automatic Property Generation
9 19 Constrained-Random Verification (CRV)
9 20 Interval Property Checking
9 21 Coverage-Driven Verification
9 22 on-the-fly instruction stream generation
9 23 Constraint Programming
9 24 Counterexample Shrinking
8 25 Multi-Armed Bandit (MAB)
8 26 Fuzzing
8 27 Squash (order-decoupled fusion)
8 28 constrained-random test generation
8 29 Instruction Scheduling
8 30 Batch (tight packing of verification events)
8 31 Model-Based Test Generation
7 32 Coverage-guided Aging
7 33 Test Case Shrinking
7 34 constraint-based test generation
7 35 Architecture Description
7 36 Burch-Dill Correspondence Checking
7 37 Replay (lightweight debugging by event retransmission)
7 38 Constrained-Random Stimulus Generation
7 39 Stimulus Template
7 40 Multicore Parallelization
7 41 Top-Down Stimulus Planning
7 42 Register-Coverage Guided Fuzzing
7 43 constrained random verification
7 44 hardware fuzzing
7 45 Model-based Stimuli Generation
7 46 Coverage-based Greybox Fuzzing
7 47 ISS Code Generation
6 48 Pipeline Modeling
6 49 Bounded Model Checking
6 50 Mapping Functions
6 51 Randomized Instruction Generation
6 52 RTL Fuzzing
6 53 Ant Colony Optimization
6 54 Generic Simulation Method
6 55 Instruction Morphing
6 56 Statistical Fault Injection (SFI)
6 57 Directed Test
6 58 Hardware-Software Co-Verification
6 59 Just-in-Time Compiled Simulation
6 60 REVERSI
6 61 Instruction Stream Generation
6 62 Register Allocation
6 63 Symbolic Execution
5 64 Code Generation
5 65 Translation Buffer
5 66 multiplexer toggle coverage
5 67 satisfiability modulo theories
5 68 Constraint Satisfaction Problem Solving
5 69 Cross-Level Testing
5 70 Directed-Random Test Sequence Generation
5 71 Constraint-Based Randomization
5 72 CPU-assisted test-case generation
5 73 AI-Driven Test Generation
5 74 Design-for-Test (DfT)
5 75 Hardware-based Seed Selection
5 76 Directed-Random Stimulus
5 77 congestor
4 78 CI/CD pipeline
4 79 Tandem Verification
4 80 code-based test generation
4 81 Instruction Scenario Modeling
4 82 Consistency Assertions
4 83 UCB1 Algorithm
4 84 Model-Based Verification
4 85 Instruction Selection
4 86 Bayesian network-based test generation
4 87 differencing (event field delta compression)
4 88 Random Test Program Generation
4 89 Constraint-based Random Stimuli Generation
4 90 Feedback-Based Verification
4 91 Random Sequence Generation
4 92 event fusion
4 93 SystemVerilog Assertions
4 94 table mutator
4 95 constrained-random instruction generation
4 96 Directed-Random Test Generation
4 97 Coverage-Driven Instruction Generation
4 98 Smart Shrinking
4 99 Interpretive Simulation
4 100 Model-Based Test Program Generation
4 100 of 365 shown
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