Constrained-random testing

Technique

Constrained-random testing is a hardware verification technique in which randomized stimuli are biased, via constraints, toward interesting, hard-to-reach, and yet-untested design logic. Constraints are typically written manually to direct randomness, but as verification progresses most generated tests yield diminishing coverage gains. Open-source generators such as RISCV-DV implement constrained-random test generation for RISC-V processor verification, producing assembly programs that target edge cases like misaligned instructions, register dependencies, pipeline hazards, memory access violations, and unhandled interrupts.

First seen 6/14/2026

Last seen 7/5/2026

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Constrained-random testing

Overview

Constrained-random testing is one of the most widely adopted methods for generating stimuli for simulation-based hardware verification. Randomness provides test diversity, but tests tend to repeatedly exercise the same design logic. To address this, constraints — typically written manually — are used to bias random tests toward interesting, hard-to-reach, and yet-untested logic in the design under test (DUT).

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RELATIONSHIPS

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LLM4DV ← compares with 98% 2e

The paper compares LLM4DV to traditional constrained-random testing.

riscv-dv ← implements 90% 1e

The methodology uses Google’s RISCV-DV to produce constrained-random assembly tests as part of verification.

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CITATIONS

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6 citations — click to expand

[1] Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based verification, where constraints (typically written manually) bias random tests toward interesting, hard-to-reach, and yet-untested logic. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[2] As verification progresses, most constrained random tests yield little to no effect on functional coverage, motivating approaches that randomly generate many tests and simulate only an effective subset. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[3] RISCV-DV automatically generates constrained-random assembly programs that target edge cases such as misaligned instructions, register dependencies (RD/RS), pipeline hazards, memory access violations, and unhandled interrupts. Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM

[4] RISCV-DV is an open-source instruction stream generator, part of Google's DV project, built on SV/UVM, supporting RV32IMAFDC/RV64IMAFDC, multiple privileged modes, page-table randomization, CSR setup randomization, and trap/interrupt handling, configurable via YAML files. Reinforcement Learning Framework for RISC-V Functional Verification

[5] The NaxRiscv verification framework integrates RISCV-DV-driven constrained-random test generation with cycle-accurate Verilator simulation, Spike golden-model co-simulation, and Questa/UVM coverage analysis, synchronized through the RISC-V Lock-Step (RVLS) framework. Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM

[6] A Jenkins-based CI pipeline automates regression testing and dynamically scales RISCV-DV test generation until predefined coverage targets are met. Comprehensive Lockstep Verification for NaxRiscv SoC integrating RISCV-DV, RVLS, and Questa/UVM