RISCV-DV
ToolRISCV-DV is the CHIPS Alliance-hosted chipsalliance/riscv-dv project, originally contributed by Google as an open-source SystemVerilog/UVM-based constrained-random instruction generator for RISC-V processor verification. It generates randomized RISC-V assembly programs that are co-simulated against an instruction-set simulator reference model, and is widely used as a stimulus-generation component (including multi-hart test generation) in academic and industrial RISC-V verification flows such as LowRISC Ibex, OpenHW CORE-V, CVA6, NaxRiscv, and FLAME. On its own it is characterized as a stimulus-generation component rather than a complete verification strategy, and is used as a teaching topic in industry CPU-verification training programs.
First seen 5/24/2026
Last seen 9/30/2026
Evidence 169 chunks
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RISCV-DV
Overview
RISCV-DV is the CHIPS Alliance-hosted chipsalliance/riscv-dv project, described in public repository metadata as a "Random instruction generator for RISC-V processor verification." Repository metadata reports Python as the project language, with 1,358 stars, 400 forks, and an update timestamp of 2026-09-30T12:52:50Z.[1]
NEIGHBORHOOD
4 nodes · 4 edgesgraph · riscv-dv · depth=1
RELATIONSHIPS
50 connectionsriscv-dv is built on SV/UVM methodology.
RISCV-DV is authored by Google.
TestRIG is compared against RISCV-DV as an alternative test generation framework.
riscv-dv is an SV/UVM based open source instruction generator that generates random instruction chains for RISC-V processors.
QCVEngine is compared against RISCV-DV for coverage and counterexample complexity.
RISCV-DV was originally developed by Google and is now maintained by the CHIPS Alliance.
riscv-dv is implemented as a collection of SystemVerilog classes.
riscv-dv is an instruction generator specifically for RISC-V processors.
MorFuzz is compared against riscv-dv in terms of coverage and performance.
riscv-dv uses Spike as a reference ISS for comparing execution results.
RISCV-DV is implemented using UVM.
RISCV-DV generates RISC-V instruction streams based on constrained-random descriptions using UVM.
riscv-dv was originally developed for Google's own needs.
RISCV-DV uses directed-random test-sequence generation to create RISC-V test programs.
riscv-dv is authored and maintained by CHIPS Alliance.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← compares with 90% 4e
The paper compares its approach with RISC-V DV in terms of efficiency.
As the ISG referenced by [4], riscv-dv provides random instruction generation across multiple levels.
The paper compares TestRIG with RISCV-DV in terms of coverage and counterexample complexity.
Google developed and open-sourced RISCV-DV
RISCV-DV supports co-simulation with sail-riscv.
The paper uses Google's riscv-dv tool to generate random tests for evaluation.
riscv-dv is a SystemVerilog/UVM-based random instruction generator, implementing the instruction-stream generator concept.
RISCV-DV is implemented using SystemVerilog (SV).
RISCV-DV serves as a random instruction generator for RISC-V verification.
RISCV-DV uses constrained-random descriptions for instruction stream generation
RISCV-DV is described as Google's constrained-random generator.
RISCV-DV supports co-simulation with riscv-ovpsim.
The paper describes using RISCV-DV for random test generation.
The paper provides an overview, evaluation and discussion of CRV for RISC-V based on the RISC-V DV framework.
RISCV-DV detects divergence by comparing execution traces between a golden model and a processor under development.
RISCV-DV is a directed-random test sequence generator for RISC-V.
The CI/CD infrastructure uses RISCV-DV to generate random tests in its pipelines.
RISCV-DV supports co-simulation with multiple ISS
RISCV-DV generates tests targeting the RISC-V Vector extension instructions.
The paper mentions RISCV-DV as a related constraint-based RISC-V verification tool.
RISCSmith is directly compared with RISCV-DV in experiments, outperforming it in bugs found and coverage.
riscv-dv provides an instruction stream generation flow within a UVM-based DV environment and is used to generate tests for RTL simulation.
RISC-V DV compiles assembly tests into RISC-V binary ELF files.
RISC-V DV generates test programs as RISC-V assembly.
RISC-V DV implements constraint-based test generation using SystemVerilog constraints.
The parallelized RISCV-DV port is coded in eUVM.
RISCV-DV is used within the UVM verification flow to generate random test programs.
RISC-V DV uses VPs as simulation backends.
basic_arithmetic_test is one of the test strategies provided by RISC-V DV.
RISCV-DV employs constrained-random generation within the SystemVerilog UVM framework.
RISCV-DV provides a functional coverage flow
RISCV-DV uses instruction registry to register RISC-V instructions with the generator.
RISCV-DV generates RISC-V instruction streams based on constrained-random descriptions.
RISCV-DV implements a handshaking mechanism for testbench communication
RISC-V DV is a CRV framework implementing constrained random verification for RISC-V.
LINKED ENTITIES
1 linksCITATIONS
6 sources6 citations — click to expand
[1] Repository metadata describes RISCV-DV as a random instruction generator for RISC-V processor verification, with 1,358 stars, 400 forks, Python as the project language, and an update timestamp of 2026-09-30T12:52:50Z. chipsalliance/riscv-dv
[2] The Alpinum Consulting RISC-V Software Ecosystem announcement describes the live-online 2026 program as covering architectures and microarchitectures, ISA and toolchains, riscv-dv instruction stream generation, CPU integration, SoC feature verification, debug, coverage, and sign-off. The RISC-V Software Ecosystem
[3] The Alpinum Consulting Part 1 'Introduction to CPU and CPU Verification' training covers instruction stream generation and open-source tools such as riscv-dv, alongside CPU architectures, microarchitecture, hierarchical verification strategies at the unit, CPU, and system levels, functional coverage modeling, and practical verification exercises. Get tickets – On-Demand recordings access | Part 1: Introduction to CPU and CPU Verification
[4] The DVCon Europe paper 'Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification' cites the Google riscv-dv repository (https://github.com/google/riscv-dv) and acknowledges the Ibex development team at LowRISC. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification
[5] The 2020 Imperas RISC-V Global Forum talk describes the OpenHW RISC-V DV flow for CV32/64 cores as a UVM environment that uses Google RISCV-DV as the random instruction generator, GCC + elf2hex to build hexfiles loaded into Instruction Memory, and a step-and-compare against a UVM RISC-V reference model invoked via `make SIMULATOR=<sim> +UVM_TEST=riscv-dv-test`, with Imperas as the RISC-V golden reference model and with Vector and Bitmanip extension support described as not yet publicly released at that time. [PDF] Imperas verification RISC-V Global Forum 2020 v3
[6] The 2020 Imperas RISC-V Global Forum case study identifies LowRISC Ibex as a small 32-bit RISC-V CPU core (RV32IMC/EMC) with a two-stage pipeline, previously known as zero-risky (PULP), and links to https://github.com/lowRISC/ibex. [PDF] Imperas verification RISC-V Global Forum 2020 v3