RISCV-DV
ToolRISCV-DV is the CHIPS Alliance-hosted `chipsalliance/riscv-dv` project, originally contributed by Google. It is a UVM-based, coverage-driven constrained-random instruction generator for RISC-V processor verification, integrated into ISS-co-simulation flows and used by multiple RISC-V core projects including VeeR EL2, Ibex, and NaxRiscv.
First seen 5/24/2026
Last seen 7/19/2026
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RISCV-DV
Overview
RISCV-DV is the CHIPS Alliance-hosted chipsalliance/riscv-dv project, described in public repository metadata as a "Random instruction generator for RISC-V processor verification." The same metadata lists Python as the repository language and reports 1,319 stars, 387 forks, and an update timestamp of 2026-07-02T12:12:27Z.[1]
NEIGHBORHOOD
19 nodes · 44 edgesgraph · riscv-dv · depth=1
RELATIONSHIPS
50 connectionsTestRIG is compared against RISCV-DV as an alternative test generation framework.
riscv-dv is built on UVM (SystemVerilog/UVM-based).
RISCV-DV is an open-source project created by Google.
RISCV-DV is a random instruction generator
QCVEngine is compared against RISCV-DV for coverage and counterexample complexity.
riscv-dv is implemented as a collection of SystemVerilog classes.
MorFuzz is compared against riscv-dv in terms of coverage and performance.
The paper describes using RISCV-DV for random test generation.
RISCV-DV uses spike as an ISS for co-simulation
The paper compares TestRIG with RISCV-DV in terms of coverage and counterexample complexity.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← compares with 90% 4e
The paper compares its approach with RISC-V DV in terms of efficiency.
RISC-V DV targets the RISC-V ISA for its verification environment.
RISCV-DV is described as Google's constrained-random generator.
RISCV-DV is built on the UVM methodology
Google developed and open-sourced RISCV-DV
RISCV-DV uses directed-random test-sequence generation to create RISC-V test programs.
RISCV-DV serves as a random instruction generator for RISC-V verification.
RISC-V DV leverages constrained-random specifications for test generation.
The paper uses Google's riscv-dv tool to generate random tests for evaluation.
RISCV-DV is implemented using SystemVerilog
The paper provides an overview, evaluation and discussion of CRV for RISC-V based on the RISC-V DV framework.
RISCV-DV is a directed-random test sequence generator for RISC-V.
The CI/CD infrastructure uses RISCV-DV to generate random tests in its pipelines.
RISCV-DV was originally developed by Google.
RISCV-DV detects divergence by comparing execution traces between a golden model and a processor under development.
RISCV-DV is an open-source constrained-random generator for RISC-V.
RISCV-DV uses riscv-ovpsim as an ISS for co-simulation
RISCV-DV supports co-simulation with multiple ISS
RISCV-DV supports sail-riscv as an ISS option
RISCV-DV generates tests targeting the RISC-V Vector extension instructions.
RISCSmith is directly compared with RISCV-DV in experiments, outperforming it in bugs found and coverage.
RISCV-DV implements a handshaking mechanism for testbench communication
The parallelized RISCV-DV port is coded in eUVM.
RISCV-DV is used within the UVM verification flow to generate random test programs.
RISCV-DV generates RISC-V instruction streams based on constrained-random descriptions.
RISCV-DV uses instruction registry to register RISC-V instructions with the generator.
RISCV-DV employs constrained-random generation within the SystemVerilog UVM framework.
RISCV-DV supports the RV32IMAFDC instruction set
The UVM environment uses RISCV-DV to generate random RISC-V assembly tests for vector instruction testing.
RISC-V DV is a CRV framework implementing constrained random verification for RISC-V.
The paper evaluates RISCV-DV performance and presents optimization techniques.
RISCV-DV categorizes execution use-cases into directed streams that are randomized and inserted into the main dump.
RISCV-DV supports running full regression tests
riscv_instr_sequence.sv is a source file that is part of the riscv-dv tool
RISCV-DV is published and maintained by CHIPS Alliance on GitHub.
A parallelized fork is used in RISCV-DV to mitigate bottlenecks in instruction stream generation.
riscv_instruction_sequence is a helper class within riscv-dv.
RISCV-DV supports ISS simulation flow
RISCV-DV supports the RV64IMAFDC instruction set
The generate_directed_instr_stream function is part of the RISCV-DV generator.
LINKED ENTITIES
2 linksCITATIONS
13 sources13 citations — click to expand
[1] RISCV-DV is hosted at chipsalliance/riscv-dv and described as a 'Random instruction generator for RISC-V processor verification' with 1,319 stars and 387 forks as of 2026-07-02. chipsalliance/riscv-dv GitHub repository metadata
[2] CHIPS Alliance describes RISCV-DV as an SV/UVM-based framework contributed by Google for RISC-V CPU verification, including privileged-mode and trap/interrupt verification, and originally located at github.com/google/riscv-dv before relocation to CHIPS Alliance. CHIPS Alliance SV Tools Project launch / Semiconductor Engineering
[3] A GLSVLSI 2021 paper characterizes Google's RISC-V DV as using SystemVerilog together with UVM to continuously generate RISC-V instruction streams from constrained-random specifications. EPEX: Processor Verification by Equivalent Program Execution (GLSVLSI 2021) reference within HARTBREAKER paper
[4] In the CHIPS Alliance co-simulation flow, RISCV-DV-generated instructions are executed on the core under test and a reference ISS (Spike or Renode), with register-writeback state compared after each instruction. CHIPS Alliance SV Tools Project launch
[5] RISCV-DV targets RV32/64IMAFDC across machine, supervisor, and user privilege modes and deliberately exercises misaligned instructions, register dependencies, pipeline hazards, memory access violations, and unhandled interrupts. Ighilahriz & Savry, RISC-V Summit Europe 2025 NaxRiscv lockstep verification paper
[6] RISCV-DV embeds a UVM functional coverage model covering opcodes, extensions (F, D, C), and CSR interactions. Ighilahriz & Savry, RISC-V Summit Europe 2025
[7] RISCV-DV is described as the only tool capable of automated generation of multi-hart test cases, and HARTBREAKER experiments used RISCV-DV's default multi-hart target configured for 64-bit designs with three harts on a triple-hart BOOM CPU. HARTBREAKER: Deterministic Fuzzing of Multi-Hart RISC-V CPUs (ISCA 2026), ETH Zurich
[8] HARTBREAKER compares RISCV-DV coverage and reports HARTBREAKER reaches comparable coverage faster, while adding IPI support, memory-model checking, and deterministic interrupt injection that RISCV-DV lacks. HARTBREAKER paper coverage comparison
[9] RISCV-DV experiments are run using the UVM framework with a commercial simulator, using Spike as a golden reference model. HARTBREAKER paper experimental setup
[10] OpenHW CORE-V verification documentation describes riscv-dv as SystemVerilog classes extending uvm_object, with COREV-DV providing a library of extensions to the Google riscv-dv generator, allowing per-core vendored copies. OpenHW Group CORE-V Verification Strategy documentation, COREV-DV
[11] CHIPS Alliance reports RISCV-DV co-simulation has been used in verification workflows for VeeR EL2 and Ibex. CHIPS Alliance SV Tools Project launch
[12] The NaxRiscv paper integrates RISCV-DV with Verilator-based RTL simulation, Spike, RVLS, and Questa/UVM-based coverage collection into a Jenkins-driven CI that scales RISCV-DV test generation until coverage targets are met. Ighilahriz & Savry, RISC-V Summit Europe 2025 NaxRiscv paper
[13] A Semiconductor Engineering excerpt on UVM functional coverage for RISC-V cores characterizes RISCV-DV as an open-source project enabling coverage-driven simulation based on UVM constrained random methods compliant with the UVM standard. Universal Verification Methodology Coverage for Bluespec RISC-V Cores (Semiconductor Engineering)