RISCV-DV
ToolRISCV-DV is the `chipsalliance/riscv-dv` GitHub-hosted random instruction generator for RISC-V processor verification. The repository is implemented primarily in Python and, in the supplied public metadata, has 1,308 stars, 385 forks, and an update timestamp of 2026-05-30T08:35:22Z.
First seen 5/24/2026
Last seen 6/8/2026
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RISCV-DV
Overview
RISCV-DV is represented in the supplied public context by the GitHub repository chipsalliance/riscv-dv. The repository is described as a “Random instruction generator for RISC-V processor verification.” The same metadata identifies Python as the repository language and reports 1,308 stars, 385 forks, and an update timestamp of 2026-05-30T08:35:22Z.[1]
NEIGHBORHOOD
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50 connectionsTestRIG is compared against RISCV-DV as an alternative test generation framework.
QCVEngine is compared against RISCV-DV for coverage and counterexample complexity.
RISC-V DV uses UVM as part of its SystemVerilog/UVM test generation infrastructure.
riscv-dv is a random instruction generator implementing random instruction generation for RISC-V verification.
RISC-V DV uses SystemVerilog for its constraint-based test generator.
RISC-V DV was created by Google.
MorFuzz is compared against riscv-dv in terms of coverage and performance.
The paper compares TestRIG with RISCV-DV in terms of coverage and counterexample complexity.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← compares with 90% 4e
The paper compares its approach with RISC-V DV in terms of efficiency.
The paper uses Google's riscv-dv tool to generate random tests for evaluation.
The paper describes using RISCV-DV for random test generation.
RISCV-DV uses directed-random test-sequence generation to create RISC-V test programs.
RISCV-DV implements constrained-random test generation for RISC-V designs.
The paper provides an overview, evaluation and discussion of CRV for RISC-V based on the RISC-V DV framework.
RISCV-DV generates test sequences for RISC-V processors.
RISCV-DV is a directed-random test sequence generator for RISC-V.
RISCV-DV generates tests targeting the RISC-V Vector extension instructions.
RISCV-DV detects divergence by comparing execution traces between a golden model and a processor under development.
The CI/CD infrastructure uses RISCV-DV to generate random tests in its pipelines.
RISC-V DV implements constraint-based test generation using SystemVerilog constraints.
RISC-V DV generates test programs as RISC-V assembly.
RISC-V DV is actively developed by Google.
riscv_instr_sequence.sv is a source file that is part of the riscv-dv tool
RISC-V DV is a CRV framework implementing constrained random verification for RISC-V.
RISCV-DV uses instruction registry to register RISC-V instructions with the generator.
RISC-V DV uses VPs as simulation backends.
The parallelized RISCV-DV port is coded in eUVM.
RISCV-DV was developed by Google as a random instruction generator.
RISCV-DV is used within the UVM verification flow to generate random test programs.
RISC-V DV compiles assembly tests into RISC-V binary ELF files.
basic_arithmetic_test is one of the test strategies provided by RISC-V DV.
The paper mentions RISCV-DV as a related constraint-based RISC-V verification tool.
RISCV-DV implements constrained-random test generation for RISC-V assembly tests
The paper evaluates RISCV-DV performance and presents optimization techniques.
riscv_instr_gen_config is a configuration class within riscv-dv.
RISCV-DV categorizes execution use-cases into directed streams that are randomized and inserted into the main dump.
riscv_instruction_sequence is a helper class within riscv-dv.
RISCV-DV tests are executed on Spike simulator for trace measurement.
A parallelized fork is used in RISCV-DV to mitigate bottlenecks in instruction stream generation.
The generate_directed_instr_stream function is part of the RISCV-DV generator.
riscv-dv is used to perform RTL verification of RISC-V IP.
riscv_asm_program_gen is a core class within riscv-dv.
riscv-dv is built on a SV UVM-based class structure.
The gen_instr function is part of the RISCV-DV generator.
riscv-dv is Google's random instruction generator tool for RISC-V verification.
riscv-dv generates complete RISC-V assembly programs for verification.
RISCV-DV uses lazy merging to reduce algorithmic complexity of directed stream insertion from O(n²) to O(n).
CHIPS Alliance developed and open-sourced the riscv-dv random instruction generator.
The UVM environment uses RISCV-DV to generate random RISC-V assembly tests for vector instruction testing.
rand_instr_test is one of the test strategies provided by RISC-V DV.
LINKED ENTITIES
5 linksTestRIG COMPARES_WITH Extracted graph relationship
Directed-Random Test Sequence Generation USES Extracted graph relationship
Execution Trace Comparison USES Extracted graph relationship
Randomized Testing of RISC-V CPUs using Direct Instruction Injection COMPARES_WITH Extracted graph relationship
MorFuzz COMPARES_WITH The MorFuzz paper explicitly compares MorFuzz against riscv-dv as a constrained instruction generator and reports relative state-coverage and time-to-coverage results.
CITATIONS
4 sources4 citations — click to collapse
[1] RISCV-DV is represented by the `chipsalliance/riscv-dv` GitHub repository, described as a random instruction generator for RISC-V processor verification. chipsalliance/riscv-dv
[2] The supplied GitHub metadata identifies Python as the repository language and reports 1,308 stars, 385 forks, and an update timestamp of 2026-05-30T08:35:22Z. chipsalliance/riscv-dv
[3] The MorFuzz paper refers to riscv-dv as a famous constrained instruction generator and uses it as a comparison baseline. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
[4] The MorFuzz evaluation reports up to 1.6× more state coverage than riscv-dv and states that MorFuzz reached in about 2.4 hours the coverage that riscv-dv took 24 hours to complete. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation