RV64IMAFDC

Concept

RV64IMAFDC is identified in the RISCV-DV project documentation as one of the supported RISC-V instruction sets for its SystemVerilog/UVM-based open-source instruction generator used in RISC-V processor verification.

First seen 5/26/2026

Last seen 8/4/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

RV64IMAFDC is listed as a supported RISC-V instruction set in RISCV-DV, an open-source instruction generator for RISC-V processor verification built with SystemVerilog and UVM. In the cited RISCV-DV documentation, the supported instruction sets are stated as RV32IMAFDC and RV64IMAFDC. [Supported instruction set]

Verification context

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections

riscv-dv ← implements 98% 2e

RISCV-DV supports the RV64IMAFDC instruction set

riscv-dv ← uses 1e

RISCV-DV supports the RV64IMAFDC instruction set.

CITATIONS

3 sources

3 citations — click to collapse

[1] Supported instruction set chipsalliance/riscv-dv

[2] RISCV-DV feature scope chipsalliance/riscv-dv

[3] RISCV-DV tool requirements chipsalliance/riscv-dv