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RV64IMAFDC

Concept WIKI v1 · 5/26/2026

RV64IMAFDC is identified in the RISCV-DV project documentation as one of the supported RISC-V instruction sets for its SystemVerilog/UVM-based open-source instruction generator used in RISC-V processor verification.

Overview

RV64IMAFDC is listed as a supported RISC-V instruction set in RISCV-DV, an open-source instruction generator for RISC-V processor verification built with SystemVerilog and UVM. In the cited RISCV-DV documentation, the supported instruction sets are stated as RV32IMAFDC and RV64IMAFDC. [Supported instruction set]

Verification context

Within RISCV-DV, RV64IMAFDC is supported as a target instruction set for generated verification programs. The generator is described as supporting features such as privileged modes, page-table randomization and exceptions, CSR setup randomization, trap and interrupt handling, MMU stress testing, illegal and HINT instruction generation, randomized branch instructions, directed-instruction mixing, debug-mode support, instruction-generation coverage, and co-simulation with multiple instruction-set simulators. [RISCV-DV feature scope]

Tool requirements

Running RISCV-DV requires an RTL simulator with SystemVerilog and UVM 1.2 support. The documentation states that the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. [RISCV-DV tool requirements]

Notes

The provided evidence identifies RV64IMAFDC as a supported instruction-set configuration but does not define the individual components of the RV64IMAFDC name.

CITATIONS

3 sources
3 citations
[1] Supported instruction set chipsalliance/riscv-dv
[2] RISCV-DV feature scope chipsalliance/riscv-dv
[3] RISCV-DV tool requirements chipsalliance/riscv-dv