sail-riscv — STIMSMITH

sail-riscv

Tool

No technical evidence or public context was provided for sail-riscv, so no verified description, capabilities, usage, or relationships can be documented.

First seen 5/25/2026

Last seen 9/5/2026

Evidence 26 chunks

Wiki v1

WIKI

Overview

No evidence was provided for sail-riscv. Because this article is restricted to the supplied evidence only, there is not enough information to describe what the tool does, how it is used, its architecture, supported workflows, or related entities.

Evidence limitations

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NEIGHBORHOOD

7 nodes · 17 edges

graph · sail-riscv · depth=1

RELATIONSHIPS

22 connections

riscv-dv ← uses 97% 4e

RISCV-DV supports co-simulation with sail-riscv.

FP-RVVTS ← uses 100% 3e

FP-RVVTS uses Sail RISC-V as the golden reference model for differential verification.

Closing the RISC-V compliance gap: Looking from the negative testing side ← evaluates 100% 2e

The paper evaluates sail-riscv simulator for compliance testing.

instruction validity checking uses → 100% 2e

Sail-RISC-V has issues with RVV instruction validity checking under dynamic configurations

Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior ← evaluates 100% 2e

The paper evaluates Sail-RISC-V's RVV behavior against Spike

spike compares with → 100% 2e

Sail-RISC-V is compared against Spike as golden reference

Test-Set Generation Sub-Flow ← uses 100% 2e

The Test-Set Generation Sub-Flow executes generated tests on Sail RISC-V for validation.

RISC-V Vector Tests Generator uses → 100% 2e

Sail-RISC-V uses the RISC-V Vector Tests Generator as its default framework for RVV testing.

RISC-V implements → 100% 1e

Sail RISC-V is the formal executable specification of the RISC-V architecture adopted by RISC-V International.

Sail-RISC-V and Spike for RISC-V Vector: Toward Consistent Golden Reference Behavior ← compares with 100% 1e

The paper compares Sail-RISC-V against Spike

RISC-V International published by → 100% 1e

Sail RISC-V is the formal specification adopted by RISC-V International.

executable specification implements → 100% 1e

Sail-RISC-V generates an executable specification for RISC-V

Formal Specification implements → 100% 1e

Sail-RISC-V is grounded in a formal specification approach

saturation flag mentions → 90% 1e

Sail-RISC-V has a bug where it does not set the saturation flag correctly

Design Under Test ← mentions 90% 1e

Sail-RISC-V is used as Design Under Test in RVVTS evaluation

Co-simulation ← uses 1e

Co-simulation in RISCV-DV uses sail-riscv as one of the supported ISS tools.

SailRunner ExecutionRunner ← uses 100% 1e

The SailRunner ExecutionRunner integrates Sail RISC-V as the golden reference for test execution and state comparison.

Instruction Set Architecture (ISA) implements → 90% 1e

SAIL-RISCV provides an executable formalization of the RISC-V ISA

run.py ← uses 96% 1e

run.py can invoke sail-riscv for ISS simulation

RVVTS ← evaluates 100% 1e

RVVTS is used to evaluate Sail-RISC-V as a Design Under Test

Dependency-Based Test-Case Minimization ← uses 95% 1e

Dependency-Based Test-Case Minimization re-executes test cases on Sail RISC-V to obtain the pre-failure machine state.

RISC-V Vector extension implements → 100% 1e

Sail-RISC-V implements the RISC-V Vector Extension 1.0