Instruction Set Architecture (ISA)
ConceptAn Instruction Set Architecture (ISA) describes the instruction-level capabilities exposed by a processor or accelerator implementation. Across the provided evidence, an ISA can take the form of named base architectures plus extensions (RISC-V: RV32I, RV64I, RV128I), a set of operation kinds and functional classes used to drive verification modeling (MIPS-I: no operation, load/store, computational, control), a transparent abstraction for specialized accelerators (a processing-in-memory DNN accelerator ISA used by the PIMCOMP-NN compiler and PIMSIM-NN simulator), the target of testability research spanning AI-driven test generation, statistical fault injection, system-level testing, design-for-test architectures, and hardware-software co-verification, and a contract that is checked between an instruction-set simulator (ISS) and an RTL implementation through symbolic-execution-based cross-level verification that distinguishes RTL errors, ISS errors, and ISA-permitted implementation mismatches (as demonstrated on the MicroRV32 RV32I+CSR core using the KLEE engine). The ISA is also the unit at which software portability must be addressed, motivating benchmarks for cross-ISA software package build repair.
First seen 5/28/2026
Last seen 7/12/2026
Evidence 50 chunks
Wiki v6
WIKI
Overview
An Instruction Set Architecture (ISA) describes the instruction-level capabilities exposed by a processor or accelerator implementation. Across the provided evidence, the ISA plays multiple principal roles:
- It names and structures processor capabilities, as in RISC-V base ISAs plus extensions.
- It defines the operation kinds and functional classes that drive a verification model, as in the MIPS-I case study used to motivate Constrained-Random Verification (CRV).
- It serves as the abstraction for specialized accelerators, such as the proposed ISA for processing-in-memory (PIM) deep neural network (DNN) accelerators.
- It is the target of testability research, including AI-driven test generation, statistical fault injection, system-level testing, design-for-test (DfT) architectures, and hardware-software co-verification.
- It is the reference contract checked between an instruction-set simulator (ISS) and an RTL implementation through symbolic-execution-based cross-level verification, with results classified as RTL errors, ISS errors, or ISA-permitted implementation mismatches.
- It functions as a unit of portability, with software package build repair being a critical task during migration across ISAs.
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
15 connectionsMIPS-I is used as the example ISA for the design under test in this verification methodology.
Simulation-based validation typically uses test programs generated at ISA level
ILA generalizes the ISA for accelerators as well as processors
The NOP instruction is part of the MIPS instruction set architecture.
Cascade takes ISA extensions as input for program generation
RISC-V is an instruction set architecture.
Stimulus generation requires intelligence about the processor's instruction set architecture.
The paper uses ISA templates to construct instruction sequences for simulation.
AES block RTL implements the AES accelerator behavior defined in the ILA/ISA
RVV is part of the RISC-V instruction set architecture.
RISC-V is described as an open and royalty-free Instruction Set Architecture.
The opcode class encapsulates operation kinds as defined by the ISA.
RISC-V defines multiple ISA variants
CRV requires intelligence about the processor ISA to generate useful stimulus.
RV32I defines integer calculations, program control, load/store and debugging instructions.
LINKED ENTITIES
1 linksCITATIONS
13 sources13 citations — click to expand
[1] An ISA names and structures processor capabilities via a base ISA plus extensions; a 32-bit RISC-V core with multiplication, CSR, Fence, and compressed support is named RV32IMCZicsrZifencei, and the three RISC-V integer base ISAs are RV32I (32-bit), RV64I (64-bit), and RV128I (128-bit). Previous wiki version 5 (RISC-V structure section)
[2] The MIPS-I instruction set is organized into four functional classes: no operation, load and store, computational, and control; an object-oriented SystemVerilog stimulus model represents operations, instructions, and instruction scenarios as classes with properties, constraints, and methods. Previous wiki version 5 (MIPS-I section)
[3] The cross-level processor-verification evidence defines six RISC-V coverage-point groups (Arithmetic, Control Flow, Memory, Special & System, CSR, Other) whose cross-product yields 36 coverage points; Coverage-guided Aging uses a Coverage-Observer and Instruction-Injector to keep randomized streams consistent across ISS and RTL. Previous wiki version 5 (RISC-V coverage groups section)
[4] RISC-V testability advances cover AI-driven and fuzzing-based test generation (including a deep RL framework achieving 95.4% average coverage and DifuzzRTL differential fuzzing), statistical fault injection via gem5-MARVEL and the FPGA-based Chiffre platform, system-level testing with TestRIG, RVFI-DII, Breker RISC-V SoCReady SystemVIP, Synopsys STING, and RiESCUE, DfT (UVM-TLM co-simulation, ISS-driven verification, TSVC for RVV), and hardware-software co-verification including PFV, KLEE-based symbolic execution, FERIVer hybrid emulation, and riscv-formal. Previous wiki version 5 (RISC-V testability advances section)
[5] Open RISC-V platforms such as PULP (RI5CY) provide lightweight in-order cores with predictable timing, while Rocket and BOOM enable systematic study of speculation and timing behavior; transient execution behaviors similar to those seen on x86 and ARM can manifest in speculative RISC-V microarchitectures. Previous wiki version 5 (Open RISC-V platforms section)
[6] An ISA for processing-in-memory (PIM) DNN accelerators targets CNN and MLP inference on devices such as RRAM, flash, FeFET, and SRAM, with the trained weights programmed into the accelerator and fixed during inference; the ISA is transparent to applications and hardware, and is used by the open-source PIMCOMP-NN compiler and PIMSIM-NN simulator. Instruction Set Architecture (ISA) for Processing-in-Memory DNN Accelerators
[7] Software package build repair across ISAs is a critical task for software deployment reliability; the introduced benchmark comprises 268 real-world build failures across diverse architectures and languages, and the evaluation of six state-of-the-art LLMs shows that cross-ISA software package repair remains difficult. A Benchmark for Language Models in Real-World System Building
[8] The DATE 2023 case study performs symbolic-execution-based cross-level verification on the MicroRV32 RISC-V processor (DUT) using an ISS from the open-source RISC-V VP as reference, targeting the RV32I+CSR ISA supported by MicroRV32, with KLEE as the symbolic-execution engine. Processor Verification using Symbolic Execution (DATE 2023)
[9] MicroRV32 had previously been tested with constrained-random techniques and verified using riscv-formal (Bounded Model Checking); symbolic cross-level verification on MicroRV32 found 10 errors in the RTL core, 2 errors in the ISS, and 19 implementation mismatches between the RTL core and the ISS, with all results confirmed by the author of MicroRV32. Processor Verification using Symbolic Execution (DATE 2023)
[10] Representative MicroRV32 verification findings include: misaligned-address handling differences for LW/LH/LHU/SW/SH (RTL fully supports, ISS does not); unimplemented privileged CSRs in RTL (mhpmevent3-31, mscratch, mcounteren); trap-on-write behavior in RTL for the writable CSRs mip, mcycle, minstret, mcycleh, minstreth; and ISS-only unprivileged and machine performance counters (cycle, cycleh, instret, instreth, time, timeh, mhpmcounter3-31, mhpmcounter3-31h), with cycle-count mismatches considered expected due to the ISS's abstract, non-cycle-accurate timing model. Processor Verification using Symbolic Execution (DATE 2023)
[11] The error-injection study injected 10 representative errors (E0–E9) covering common RTL functionality: E0 is a don't-care decoding bit in SLLI (RV32I) at the 7th highest bit causing the reserved RV64I instruction to decode as SLLI; E1 and E2 mark the same don't-care bit in SRLI; E3 is a STUCK-at-0 at the lowest result bit in ADDI; E4 is a STUCK-at-0 at the highest result bit in SUB; E5 prevents JAL from changing the PC; E9 causes LW to load only the lower 16 bits of a 32-bit value. Processor Verification using Symbolic Execution (DATE 2023)
[12] With a 24-hour runtime limit and co-simulation configured for RV32I (with assumptions blocking CSR instructions), the symbolic cross-level verification found all injected errors quickly. With instruction limit 1, runs executed between 2,239,208 and 12,367,140 instructions and required 54 s to 3,237 s to find each error (median 4,237,517 instructions in 543 s; total 53,283,172 instructions in 9,685 s); with instruction limit 2, runs executed between 2,182,018 and 33,959,660 instructions and required 65 s to 21,994 s (median 4,560,215 instructions in 790 s; total 88,712,782 instructions in 37,201 s). The instruction limit of 1 was faster, suggesting the instruction limit should be set as low as possible and increased incrementally. Processor Verification using Symbolic Execution (DATE 2023)
[13] Due to the large degree of different valid implementation choices that the RISC-V ISA offers, effective methods are needed to detect mismatches in order to support the designer in providing an exactly matching configuration of ISS and RTL core. Processor Verification using Symbolic Execution (DATE 2023)