Instruction Set Architecture (ISA)
ConceptAn Instruction Set Architecture (ISA) describes the instruction-level capabilities exposed by a processor or accelerator implementation. Across the provided evidence, an ISA can take the form of named base architectures plus extensions (RISC-V: RV32I, RV64I, RV128I), a set of operation kinds and functional classes used to drive verification modeling (MIPS-I: no operation, load/store, computational, control), a transparent abstraction for specialized accelerators (a processing-in-memory DNN accelerator ISA used by the PIMCOMP-NN compiler and PIMSIM-NN simulator), or the target of testability research spanning AI-driven test generation, statistical fault injection, system-level testing, design-for-test architectures, and hardware-software co-verification.
First seen 5/28/2026
Last seen 6/9/2026
Evidence 23 chunks
Wiki v5
WIKI
Overview
An Instruction Set Architecture (ISA) describes the instruction-level capabilities exposed by a processor or accelerator implementation. Across the provided evidence, the ISA plays multiple principal roles:
- It names and structures processor capabilities, as in RISC-V base ISAs plus extensions.
- It defines the operation kinds and functional classes that drive a verification model, as in the MIPS-I case study used to motivate Constrained-Random Verification (CRV).
- It serves as the abstraction for specialized accelerators, such as the proposed ISA for processing-in-memory (PIM) deep neural network (DNN) accelerators.
- It is the target of testability research, including AI-driven test generation, statistical fault injection, system-level testing, design-for-test (DfT) architectures, and hardware-software co-verification.
- It functions as a unit of portability, with software package build repair being a critical task during migration across ISAs.
NEIGHBORHOOD
2 nodes · 2 edgesgraph · Instruction Set Architecture (ISA) · depth=1
RELATIONSHIPS
9 connectionsILA generalizes the ISA for accelerators as well as processors
MIPS-I is used as the example ISA for the design under test in this verification methodology.
RISC-V defines multiple ISA variants
CRV requires intelligence about the processor ISA to generate useful stimulus.
RV32I defines integer calculations, program control, load/store and debugging instructions.
RISC-V is an instruction set architecture.
Stimulus generation requires intelligence about the processor's instruction set architecture.
AES block RTL implements the AES accelerator behavior defined in the ILA/ISA
The opcode class encapsulates operation kinds as defined by the ISA.
LINKED ENTITIES
6 linksRISC-V instance_of RISC-V is explicitly identified as the primary ISA in the new testability evidence, with named base ISAs RV32I, RV64I, RV128I and extensions such as RV32M, RV32C, ZICSR, ZIFENCEI.
Constrained-Random Verification (CRV) related_to The testability survey explicitly builds on 'earlier constrained-random algorithm approaches' and is the basis for the cross-level processor verification evidence.
riscv-formal related_to riscv-formal is explicitly described in the new evidence as an open RISC-V formal verification framework using the RISC-V Formal Interface (RVFI).
RISC-V Formal Interface (RVFI) related_to RVFI is the interface used by riscv-formal and TestRIG (as RVFI-DII) to drive random instruction streams and formal property checks against reference ISA specifications.
DiFuzzRTL related_to DifuzzRTL is named in the new evidence as a differential fuzzing approach applied to RISC-V RTL designs to identify inconsistencies across implementations.
RISC-V Vector extension (RVV) related_to RVV is explicitly named in the new evidence as the target of TSVC-based instruction coverage methodology by Lai et al.
CITATIONS
29 sources29 citations — click to expand
[1] An ISA is the target of testability research spanning AI-driven test generation, statistical fault injection, system-level testing, design-for-test architectures, and hardware-software co-verification. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[2] Recent advances in RISC-V testability are organized into five key areas: AI-driven test generation, statistical fault injection for security assessment, system-level test innovations, design-for-test (DfT) architectures, and hardware-software co-verification. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[3] Chen et al. introduced a deep reinforcement learning framework that generates instruction sequences maximizing toggle coverage while minimizing test time, achieving 95.4% average coverage across various benchmarks. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[4] DifuzzRTL is a differential fuzzing approach applied to RISC-V RTL designs that compares multiple implementations under identical instruction sequences to identify inconsistencies. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[5] The gem5-MARVEL framework tracks fault propagation across cores and coherent memory, enabling statistical injection of transient, intermittent, and permanent fault models. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[6] The FPGA-based Chiffre platform enables real-time fault injection into RISC-V cores synthesized on adaptable hardware. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[7] Synopsys STING produces test programs that exercise privilege levels, memory protection, interrupt handling, and other system behaviors in a portable, self-checking manner across simulation, FPGA prototypes, and silicon platforms. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[8] TestRIG uses RVFI-DII interfaces to drive random instruction streams against both reference models and implementations under test, comparing execution traces to detect divergences. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[9] Breker's RISC-V SoCReady SystemVIP test suite synthesizes coverage-driven tests for multicore coherency, atomic instructions, paging, interrupts, system memory protection, and performance profiling. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[10] RiESCUE is an open-source directed test framework that facilitates customizable test generation and compliance testing for multiple RISC-V extensions. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[11] Scan-based DfT remains relevant for RISC-V cores, enabling sequential element controllability and observability during test shifts to support ATPG for structural faults. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[12] Qiu and Liu propose an integrated UVM-TLM co-simulation framework that co-verifies functional correctness alongside performance models for superscalar RISC-V cores. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[13] Galimberti et al. describe functional ISS-driven verification that interfaces a RISC-V ISS with RTL testbenches to achieve high coverage across pipeline and control flows. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[14] Lai et al. develop an instruction coverage analysis methodology based on TSVC to systematically quantify RVV (RISC-V Vector Extension) coverage. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[15] Polynomial Formal Verification (PFV) uses Binary Decision Diagrams (BDDs) to bound verification complexity and has been demonstrated on multi-cycle RISC-V cores covering combinational and sequential logic. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[16] Bruns et al. integrate the KLEE symbolic execution engine with co-simulation frameworks that couple an ISS with the RTL of a RISC-V processor under test. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[17] FERIVer is an FPGA-assisted emulation framework that accelerates RTL verification by cross-validating hardware behavior against software models on the same platform. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[18] The riscv-formal project is an open RISC-V formal verification framework that uses the RISC-V Formal Interface (RVFI) to formally check RTL models against reference ISA specifications. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[19] The PULP platform provides lightweight in-order cores such as RI5CY with simplified pipelines and predictable execution characteristics for safety-oriented embedded contexts. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[20] Rocket and BOOM are RISC-V cores with openly documented microarchitectural implementations that have enabled systematic study of speculation and timing behavior; BOOM is an out-of-order speculative processor whose open RTL allows researchers to selectively disable speculation, configure cache hierarchies, and evaluate timing interference. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[21] Recent analyses of speculative execution in RISC-V cores have shown that transient execution behavior can affect timing predictability, with similar transient behaviors to those first demonstrated on x86 and ARM. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[22] The RISC-V base integer ISAs are RV32I (32-bit), RV64I (64-bit), and RV128I (128-bit), and instruction set extensions are appended to the name of the integer base ISA to name the capabilities of a core implementation (e.g., RV32IMCZicsrZifencei). Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[23] The MIPS-I instruction set is organized into four functional classes: no operation, load and store, computational, and control; transactions are modeled with properties, constraints, and methods in SystemVerilog, and the operation class has a kind enumerated type plus a random functional-class property. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[24] For the MIPS-I BEQ operation, the opcode class is extended with a LABEL value in kind_e, a label_suffix property (e.g., LABEL_005 for the 5th line), and from/to integer properties; the relative PC offset is calculated from these two integral numbers. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[25] Cross-level RISC-V processor verification defines six coverage-point instruction groups: Arithmetic, Control Flow, Memory, Special & System, CSR, and Other; with the cross-product of six groups, 36 coverage points are defined. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[26] Coverage-guided Aging uses a Coverage-Observer and Instruction-Injector to drive legal injection of targeted instruction sequences into randomized test generators while keeping instruction streams consistent across ISS and RTL cores via shared cryptographic seeds. Towards Reliable and Secure RISC-V Systems: Survey of Testability ...
[27] An ISA for processing-in-memory (PIM) DNN accelerators targets DNN inference on PIM-based architectures where trained weights are programmed into the accelerator and fixed during inference, and is transparent to applications and hardware implementations. Instruction Set Architecture (ISA) for Processing-in-Memory DNN Accelerators
[28] The PIM DNN accelerator ISA supports CNNs and MLPs, is device-agnostic over RRAM, flash, FeFET, and SRAM, and has been used in the open-source DNN compiler PIMCOMP-NN and the open-source simulator PIMSIM-NN. Instruction Set Architecture (ISA) for Processing-in-Memory DNN Accelerators
[29] A benchmark for cross-ISA software package build repair comprises 268 real-world software package build failures across diverse architectures and languages, and provides a standardized evaluation pipeline; results show that cross-ISA software package repair remains difficult. A Benchmark for Language Models in Real-World System Building