RISC-V Vector extension (RVV)

RISC-V Vector Extension (RVV)

Concept

The RISC-V Vector Extension (RVV) is a vector extension of the open-source RISC-V ISA. The provided evidence describes RVV as vector-length agnostic, configurable for different element widths, and including vectorized arithmetic, logical, and memory instructions plus vector-specific operations such as reductions and scatter/gather. It also documents practical verification concerns for an RVV 0.7.1 vector accelerator, including RISCV-DV test generation, Spike co-simulation, vsetvli configuration, memory-operation testing, vstart retry behavior, and unordered floating-point reduction handling.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 6 chunks

Wiki v2

WIKI

Overview

The RISC-V Vector Extension (RVV) is a vector extension of the open-source RISC-V Instruction Set Architecture (ISA). A 2022 verification paper describes RISC-V as an open-source ISA with a vector extension, notes that RVV version 1.0 existed at that time, and studies a vector accelerator implementing RVV 0.7.1. [RVV ISA role and version context]

RVV includes vectorized versions of many arithmetic, logical, and memory instructions. It also includes vector-specific instructions such as reductions and scatter/gather operations. [RVV instruction categories]

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

riscv-dv ← uses 97% 3e

RISCV-DV generates tests targeting the RISC-V Vector extension instructions.

RISC-V ISA part of → 98% 2e

RVV is the vector extension of the RISC-V ISA.

spike ← uses 97% 1e

Spike is adapted to follow the RISC-V vector specification 0.7.1

RISC-V part of → 99% 1e

The RISC-V Vector Extension is part of the RISC-V ISA

vstart ← part of 93% 1e

vstart is a concept defined in the RISC-V Vector Extension specification

Unordered Floating-Point Reductions ← part of 91% 1e

Unordered floating-point reductions are part of the RVV instruction set

LINKED ENTITIES

5 links

riscv-dv USES Extracted graph relationship

spike USES Extracted graph relationship

RISC-V PART_OF Extracted graph relationship

vstart PART_OF Extracted graph relationship

Unordered Floating-Point Reductions PART_OF Extracted graph relationship

CITATIONS

19 sources

19 citations — click to expand

[1] RVV ISA role and version context Functional Verification of a RISC-V Vector Accelerator

[2] RVV instruction categories Functional Verification of a RISC-V Vector Accelerator

[3] RVV vector-length agnostic behavior and vsetvli configuration Functional Verification of a RISC-V Vector Accelerator

[4] Standard RVV vector register count and reduced-register proposals RISC-V V Vector Extension (RVV) with reduced number of vector registers

[5] RVV memory-access characterization in in-cache-computing research Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing

[6] RVV 0.7.1 accelerator implementation Functional Verification of a RISC-V Vector Accelerator

[7] Example VPU capabilities Functional Verification of a RISC-V Vector Accelerator

[8] Scalar core and VPU interaction Functional Verification of a RISC-V Vector Accelerator

[9] RVV verification infrastructure Functional Verification of a RISC-V Vector Accelerator

[10] RISCV-DV use for RVV testing Functional Verification of a RISC-V Vector Accelerator

[11] RISCV-DV RVV adaptations Functional Verification of a RISC-V Vector Accelerator

[12] Spike roles Functional Verification of a RISC-V Vector Accelerator

[13] Spike modifications Functional Verification of a RISC-V Vector Accelerator

[14] RVV reduction algorithm allowance and verification issue Functional Verification of a RISC-V Vector Accelerator

[15] Reduction reference model workaround Functional Verification of a RISC-V Vector Accelerator

[16] VPU memory-operation verification Functional Verification of a RISC-V Vector Accelerator

[17] Load and store verification behavior Functional Verification of a RISC-V Vector Accelerator

[18] vstart retry behavior Functional Verification of a RISC-V Vector Accelerator

[19] Verification outcome Functional Verification of a RISC-V Vector Accelerator