vsetvli instruction

Concept

In the cited RISC-V vector-accelerator verification work, `vsetvli` instructions were generated as part of modified RISCV-DV test programs so the tests could change vector element width and vector length.

First seen 5/28/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

vsetvli is discussed in the available evidence as an instruction that needed explicit generation in a RISC-V vector verification flow. The verification team modified RISCV-DV so generated assembly tests could include vsetvli instructions and so memory-operation generation could account for changes in element width and vector length.

Role in verification

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NEIGHBORHOOD

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RELATIONSHIPS

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Functional Verification of a RISC-V Vector Accelerator ← uses 87% 1e

RISCV-DV was extended to generate vsetvli instructions through the test code.

riscv-dv ← introduces 87% 1e

RISCV-DV was extended to generate vsetvli instructions.

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

riscv-dv INTRODUCES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] RISCV-DV was used to generate random RISC-V assembly tests for the VPU verification flow. source

[2] The authors added generation of vsetvli instructions to RISCV-DV. source

[3] The vsetvli-generation change was associated with modifications to memory-operation generation to allow changes in element width and vector length. source

[4] The RISCV-DV adaptation was needed because the available RISCV-DV implemented a later RVV version than 0.7.1. source