Constrained-Random Verification (CRV)

Technique

First seen 5/31/2026

Last seen 6/5/2026

Evidence 9 chunks

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RELATIONSHIPS

13 connections

Directed Stimulus compares with → 88% 2e

The CRV approach is supplemented by directed stimulus for specific functionalities.

Program Trace uses → 95% 1e

CRV generates program traces as the main stimulus for the processor design under test.

Top-Down Stimulus Planning uses → 93% 1e

CRV requires top-down stimulus planning to build the stimulus-generation infrastructure.

SystemVerilog Random Sequence Generator uses → 88% 1e

The SystemVerilog random sequence generator can create instruction sequences randomly but is procedural and does not fully exploit object-based randomization.

Scenario Generator uses → 90% 1e

CRV employs a scenario generator to select and randomize scenarios during stimulus generation.

Stimulus Generation uses → 95% 1e

CRV provides the ability to create useful stimulus through a stimulus-generation infrastructure.

Instruction Scenario uses → 95% 1e

CRV uses instruction scenarios as the main stimulus building blocks for processor verification.

Directed Test compares with → 88% 1e

CRV is proposed as an alternative to traditional directed tests whose creation time has become unreasonable.

SystemVerilog Random Sequence Generator compares with → 87% 1e

CRV using object-based randomization is contrasted with procedural random sequence generation.

Instruction Set Architecture (ISA) uses → 92% 1e

CRV requires intelligence about the processor ISA to generate useful stimulus.

Top-Down Stimulus Planning uses → 93% 1e

The CRV approach is paired with top-down planning to create the stimulus-generation infrastructure.

Object-Oriented Stimulus Generation uses → 93% 1e

The article proposes an object-oriented solution as the implementation approach for CRV.

Scenario Generator ← uses 90% 1e

The scenario generator applies constrained-random techniques to select and randomize scenarios.