Object-Oriented Stimulus Generation

Technique

First seen 5/29/2026

Last seen 6/5/2026

Evidence 11 chunks

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RELATIONSHIPS

19 connections

SystemVerilog uses → 97% 5e

The object-oriented solution is implemented using SystemVerilog classes and constraints.

Verification Methodology Manual (VMM) uses → 95% 2e

The object-oriented solution leverages VMM base classes from Synopsys.

Opcode Class uses → 93% 2e

Object-oriented stimulus generation uses the opcode class to encapsulate operation kind, operands, and constraints.

Instruction Class uses → 93% 2e

Object-oriented stimulus generation models instructions as classes with properties, constraints, and methods.

MIPS-I Instruction Set Architecture evaluates → 88% 2e

The object-oriented stimulus generation approach is demonstrated using a MIPS-I instruction set architecture processor as the design under test.

Exception Handling in Stimulus Generation implements → 90% 2e

The object-oriented approach implements exception handling by supporting illegal opcodes and constraint toggling for exception conditions.

Branch Scenario uses → 90% 2e

Object-oriented stimulus generation uses specialized branch scenario classes to handle forward and backward branch constraints.

Illegal Opcode Stimulus implements → 93% 1e

The operation class supports the ability to introduce illegal opcodes for exception testing.

foreach Array Constraints uses → 92% 1e

Object-oriented stimulus generation uses foreach array constraints in SystemVerilog to specify constraints over dynamic arrays of instruction objects.

Transaction Abstraction uses → 95% 1e

Object-oriented stimulus generation models operations, instructions, and scenarios as transaction classes at multiple levels of abstraction.

Design Under Test evaluates → 88% 1e

The object-oriented stimulus generation approach targets the processor as the design under test.

Design Under Test (DUT) evaluates → 90% 1e

The object-oriented stimulus generation solution is built to verify the processor DUT.

MIPS-I Instruction Set uses → 92% 1e

The solution uses a MIPS-I processor as the example DUT.

Constrained-Random Verification (CRV) ← uses 93% 1e

The article proposes an object-oriented solution as the implementation approach for CRV.

Random Sequence Generation compares with → 88% 1e

Random sequence generation is described as procedural and contrasted with object-based randomization.

VMM uses → 90% 1e

Object-oriented stimulus generation leverages VMM base classes as its foundation.

constrained random verification implements → 90% 1e

The object-oriented approach implements constrained-random verification for processor testing.

Common Instruction Scenario Base Class uses → 92% 1e

Object-oriented stimulus generation uses a common instruction scenario base class to share methods across all user-defined scenarios.

Top-Down Stimulus Planning ← part of 88% 1e

Top-down stimulus planning is one major component of the object-oriented solution.