Random Sequence Generation
TechniqueRandom Sequence Generation is a verification stimulus technique in which sequences, such as processor instruction sequences, are generated randomly according to structured rules and scenarios. In SystemVerilog-based microprocessor verification, it can improve stimulus quality compared with hand-written directed tests, but simple or purely procedural random sequencing may miss important corner cases and does not fully exploit constraint-based, object-oriented randomization.
WIKI
Overview
Random Sequence Generation is a technique for creating verification stimulus by randomly assembling sequences under a structured set of rules and scenarios. In the microprocessor-verification context described by the evidence, SystemVerilog language features such as the SystemVerilog random sequence generator can be used to create random instruction sequences and improve stimulus quality relative to manually authored directed tests. [Random sequence generation definition and purpose]
Use in processor verification
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