Verification Methodology Manual (VMM)

Tool

The Verification Methodology Manual (VMM) is referenced in the provided evidence as Synopsys’s commercially available base-class methodology for SystemVerilog constrained-random, object-oriented verification. In the cited processor-verification example, VMM-style base classes and `vmm_data` methods are used in a transaction-based stimulus model built from operations, instructions, and instruction scenarios.

First seen 5/28/2026

Last seen 6/5/2026

Evidence 12 chunks

Wiki v1

WIKI

Overview

The Verification Methodology Manual (VMM) is cited as Synopsys’s set of commercially available verification base classes used with SystemVerilog in an object-oriented constrained-random verification flow. In the cited microprocessor-verification example, the proposed solution combines top-down stimulus planning with bottom-up implementation using SystemVerilog and base classes “such as those in Synopsys’s Verification Methodology Manual, VMM.”

Role in constrained-random processor verification

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

Synopsys published by → 98% 4e

VMM base classes are provided by Synopsys.

Object-Oriented Stimulus Generation ← uses 95% 2e

The object-oriented solution leverages VMM base classes from Synopsys.

vmm_data ← part of 95% 2e

vmm_data is a standard base class that is part of the VMM methodology.

Object-Oriented Verification ← uses 95% 1e

The object-oriented verification solution uses VMM base classes from Synopsys.

Object-Oriented Verification ← uses 95% 1e

The object-oriented solution uses VMM base classes for implementation.

LINKED ENTITIES

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Object-Oriented Verification USES Extracted graph relationship

Synopsys PUBLISHED_BY Extracted graph relationship

vmm_data PART_OF Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] VMM is referenced as Synopsys’s commercially available base-class methodology used with SystemVerilog in a constrained-random processor-verification solution. Applying constrained-random verification to microprocessors

[2] The cited processor-verification flow uses object-oriented SystemVerilog classes to model operations, instructions, and instruction scenarios as transaction abstractions. Applying constrained-random verification to microprocessors

[3] A transaction class in the cited methodology is described as having properties, constraints, and methods. Applying constrained-random verification to microprocessors

[4] The example uses constraints to encode processor rules and allows separate constraint blocks to be controlled individually for legal and exception-generating stimulus. Applying constrained-random verification to microprocessors

[5] The evidence refers to implementation of standard `vmm_data` methods in an Instruction class, including display and packing methods such as `psdisplay()` and `byte_pack()`. Applying constrained-random verification to microprocessors