Synopsys

Organization

The supplied evidence presents Synopsys in semiconductor design-verification and EDA contexts. It highlights Synopsys's OpenVera contribution to SystemVerilog verification functionality, its creation of the Verification Methodology Manual (VMM), use of the Synopsys VCS constraint solver for hierarchical constrained-random microcode stimulus generation, and a RISC-V verification flow involving STING, ImperasTS, ImperasDV, VCS, Verdi, ZeBu, and HAPS.

First seen 5/25/2026

Last seen 6/8/2026

Evidence 15 chunks

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WIKI

Overview

The supplied evidence presents Synopsys primarily in an electronic design automation and semiconductor design-verification context. Synopsys is associated with verification-language and methodology work, including the OpenVera functionality contributed into SystemVerilog and the Synopsys-created Verification Methodology Manual (VMM). [C1][C2]

The evidence also describes Synopsys-related verification tooling and flows, including use of the Synopsys VCS constraint solver for constrained-random microcode stimulus generation and a RISC-V verification methodology involving STING, ImperasTS, ImperasDV, VCS, Verdi, ZeBu, and HAPS. [C3][C4]

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

Verification Methodology Manual (VMM) ← published by 98% 4e

VMM base classes are provided by Synopsys.

Synopsys VCS ← published by 95% 1e

Synopsys VCS is a product developed and published by Synopsys.

VMM introduces → 95% 1e

Synopsys created the VMM.

VMM ← published by 98% 1e

The VMM (Verification Methodology Manual) is published by Synopsys.

LINKED ENTITIES

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Verification Methodology Manual (VMM) PUBLISHED_BY Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] SystemVerilog incorporated core verification functionality predominantly supported by OpenVera, which was contributed by Synopsys; SystemVerilog became IEEE 1800-2005 and later IEEE 1800-2009 with Verilog. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] VMM was created by Synopsys as a set of practices for reusable SystemVerilog verification environments and contributed to the UVM standardization background, including VMM-RAL. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] AMD and Synopsys authors described using the Synopsys VCS constraint solver for hierarchical constrained-random microcode stimulus generation, including two-layer weighted generation and hierarchical partitioning to reduce memory requirements and improve performance. Generating AMD microcode stimuli using VCS constraint solver

[4] A RISC-V verification flow combines STING constrained-random stimulus with directed ImperasTS suites, uses portable self-checking tests across simulation, ZeBu, HAPS, and silicon, and references VCS, Verdi, ImperasDV, and Synopsys RISC-V resources. RISC-V test generation: random, directed, coverage

[5] An EE Times constrained-random verification article describes processor verification challenges, the limitations of directed and simple random tests, and an object-oriented SystemVerilog solution using commercially available base classes such as those in Synopsys's VMM. Applying constrained-random verification to microprocessors