Synopsys

Organization

The supplied evidence presents Synopsys in semiconductor design-verification and EDA contexts. It highlights Synopsys's OpenVera contribution to SystemVerilog verification functionality, its creation of the Verification Methodology Manual (VMM), use of the Synopsys VCS constraint solver for hierarchical constrained-random microcode stimulus generation, and a RISC-V verification flow involving STING, ImperasTS, ImperasDV, VCS, Verdi, ZeBu, and HAPS.

First seen 5/25/2026

Last seen 7/14/2026

Evidence 31 chunks

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WIKI

Overview

The supplied evidence presents Synopsys primarily in an electronic design automation and semiconductor design-verification context. Synopsys is associated with verification-language and methodology work, including the OpenVera functionality contributed into SystemVerilog and the Synopsys-created Verification Methodology Manual (VMM). [C1][C2]

The evidence also describes Synopsys-related verification tooling and flows, including use of the Synopsys VCS constraint solver for constrained-random microcode stimulus generation and a RISC-V verification methodology involving STING, ImperasTS, ImperasDV, VCS, Verdi, ZeBu, and HAPS. [C3][C4]

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NEIGHBORHOOD

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RELATIONSHIPS

21 connections

Verification Methodology Manual (VMM) ← published by 98% 4e

VMM base classes are provided by Synopsys.

ImperasDV ← published by 93% 2e

ImperasDV is provided via Synopsys partnership and published by Synopsys.

Synopsys ImperasDV ← published by 98% 2e

Synopsys ImperasDV is a commercial tool published by Synopsys.

Synopsys VCS ← published by 99% 2e

Synopsys VCS is published by Synopsys as an industry-standard RTL simulator.

VMM ← published by 98% 1e

The VMM (Verification Methodology Manual) is published by Synopsys.

Certitude ← published by 100% 1e

Certitude is a commercial tool from Synopsys.

Understanding UVM Coverage for RISC-V Processor Designs ← published by 90% 1e

The white paper is published by Synopsys as a white paper document.

Prabha Krishnaswami ← part of 100% 1e

Prabha Krishnaswami is a Senior Staff Applications Engineer at Synopsys.

Rohit Narkar ← part of 100% 1e

Rohit Narkar is Director of Application Engineering at Synopsys.

Amit Goldie ← part of 100% 1e

Amit Goldie is a Principal Applications Engineer at Synopsys.

Synopsys VCS uses → 90% 1e

Synopsys VCS is a product of Synopsys used in the verification flow.

Synopsys Verdi uses → 90% 1e

Synopsys Verdi is a product of Synopsys used for debug and coverage viewing.

Verification Reference Cookbook for Bluespec RISC-V Processors ← published by 95% 1e

The Verification Reference Cookbook is provided by Synopsys.

Bluespec ← compares with 80% 1e

Synopsys and Bluespec are collaborating on defining RISC-V ISA coverage methodology.

ImperasDV uses → 93% 1e

ImperasDV is integrated with Synopsys EDA SystemVerilog environments.

Verdi ← published by 99% 1e

Verdi is a debug environment published by Synopsys.

Lockstep Co-Simulation Methodology mentions → 92% 1e

Synopsys documents the lockstep co-simulation methodology for ImperasDV with retirement-level compare and integration with VCS and Verdi.

Imperas ← compares with 85% 1e

Synopsys and Imperas collaborated on SystemVerilog-based RISC-V verification co-simulation flows.

VMM introduces → 95% 1e

Synopsys created the VMM.

Imperas Software ← part of 99% 1e

Imperas Software is now part of Synopsys.

Ravindra Aneja ← part of 99% 1e

Ravindra Aneja is director of applications engineering in Synopsys' EDA Group.

LINKED ENTITIES

1 links

Verification Methodology Manual (VMM) PUBLISHED_BY Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] SystemVerilog incorporated core verification functionality predominantly supported by OpenVera, which was contributed by Synopsys; SystemVerilog became IEEE 1800-2005 and later IEEE 1800-2009 with Verilog. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] VMM was created by Synopsys as a set of practices for reusable SystemVerilog verification environments and contributed to the UVM standardization background, including VMM-RAL. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] AMD and Synopsys authors described using the Synopsys VCS constraint solver for hierarchical constrained-random microcode stimulus generation, including two-layer weighted generation and hierarchical partitioning to reduce memory requirements and improve performance. Generating AMD microcode stimuli using VCS constraint solver

[4] A RISC-V verification flow combines STING constrained-random stimulus with directed ImperasTS suites, uses portable self-checking tests across simulation, ZeBu, HAPS, and silicon, and references VCS, Verdi, ImperasDV, and Synopsys RISC-V resources. RISC-V test generation: random, directed, coverage

[5] An EE Times constrained-random verification article describes processor verification challenges, the limitations of directed and simple random tests, and an object-oriented SystemVerilog solution using commercially available base classes such as those in Synopsys's VMM. Applying constrained-random verification to microprocessors