VMM

Concept

VMM, the Verification Methodology Manual, was a Synopsys-created SystemVerilog verification methodology for building reusable verification environments. It used SystemVerilog features such as object-oriented programming, randomization, constraints, and functional coverage, and its ideas contributed to the later Accellera UVM standard, including through VMM-RAL.

First seen 5/27/2026

Last seen 5/28/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

VMM stands for Verification Methodology Manual. In the cited verification-methodology context, it was a set of practices for creating reusable verification environments in SystemVerilog. VMM was created by Synopsys and made use of SystemVerilog features including object-oriented programming, randomization, constraints, and functional coverage.

Role in SystemVerilog verification

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NEIGHBORHOOD

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RELATIONSHIPS

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UVM ← derived from 90% 2e

UVM incorporated contributions from VMM.

Synopsys ← introduces 95% 1e

Synopsys created the VMM.

LINKED ENTITIES

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UVM DERIVED_FROM Extracted graph relationship

Synopsys INTRODUCES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] VMM stands for Verification Methodology Manual and was a set of practices for creating reusable verification environments in SystemVerilog. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] VMM was created by Synopsys. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] VMM used SystemVerilog features such as object-oriented programming, randomization, constraints, and functional coverage. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] The Accellera UVM standard was built from collaboration among EDA vendors and customers and drew on the OVM code base plus contributions from VMM. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] UVM incorporated technology origins including Mentor's AVM, Mentor and Cadence's OVM, Verisity's eRM, and Synopsys's VMM-RAL, along with Resources, TLM, and Phasing. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi