Overview
VMM stands for Verification Methodology Manual. In the cited verification-methodology context, it was a set of practices for creating reusable verification environments in SystemVerilog. VMM was created by Synopsys and made use of SystemVerilog features including object-oriented programming, randomization, constraints, and functional coverage.
Role in SystemVerilog verification
The methodology appeared in the broader industry movement toward standardized, reusable verification practices for semiconductor IP. SystemVerilog provided the object-oriented and verification-oriented language mechanisms used by methodologies such as VMM, including class-based modeling and constrained-random verification concepts.
Relationship to UVM
VMM is historically important because it contributed to the standardization effort that produced UVM. The Accellera UVM standard was built from collaboration among EDA vendors and customers, drawing on the OVM code base and contributions from VMM. The resulting UVM technology mix included origins in Mentor's AVM, Mentor and Cadence's OVM, Verisity's eRM, and Synopsys's VMM-RAL, along with newer features such as Resources, TLM, and Phasing.