UVM

Concept

UVM (Universal Verification Methodology) is a hardware verification methodology described in the provided evidence as supporting structured, reusable testbenches. It is used with SystemVerilog in RISC-V DV to continuously generate constrained-random RISC-V instruction streams. Recent public research summaries identify UVM testbench construction and stimulus generation as major automation targets because they still require substantial manual coding, repeated EDA tool runs, and domain expertise.

First seen 5/25/2026

Last seen 6/7/2026

Evidence 41 chunks

Wiki v6

WIKI

UVM

UVM stands for Universal Verification Methodology. In the provided evidence, it appears as a hardware verification methodology used with SystemVerilog in RISC-V DV, where it supports constrained-random generation of RISC-V instruction streams. [C1]

Role in hardware verification

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NEIGHBORHOOD

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RELATIONSHIPS

19 connections

riscv-dv ← uses 100% 6e

RISC-V DV uses UVM as part of its SystemVerilog/UVM test generation infrastructure.

Functional Verification of a RISC-V Vector Accelerator ← uses 99% 4e

The paper describes building a UVM environment for verification

VMM derived from → 90% 2e

UVM incorporated contributions from VMM.

Accellera ← introduces 100% 2e

Accellera standardized and introduced the UVM standard.

OVM derived from → 100% 2e

UVM is derived from OVM as its core foundation.

Ibex Core ← uses 100% 2e

Ibex Core is verified using a UVM-based testbench.

riscv-dv ← implements 95% 2e

riscv-dv is built on a SV UVM-based class structure.

Core-V-Verif ← uses 100% 1e

Core-V-Verif uses UVM for developing verification test plans and environment.

UVM Transaction Level Modeling ← part of 100% 1e

UVM Transaction Level Modeling is a component of the UVM framework.

UVM Factory ← part of 100% 1e

The UVM Factory is a design pattern component of UVM.

gen-binaries.py ← part of 85% 1e

gen-binaries.py is located in the UVM directory, indicating it is part of the UVM testbench infrastructure

eUVM ← implements 100% 1e

eUVM is an opensource multicore-enabled implementation of UVM IEEE 1800.2 standard.

UVM-TLM Co-Simulation ← uses 95% 1e

UVM-TLM co-simulation uses Universal Verification Methodology.

PyUVM ← implements 90% 1e

PyUVM implements UVM methodology in Python but piggybacks on an RTL simulator for scheduling.

UVM-SystemC ← implements 90% 1e

UVM-SystemC implements UVM using the SystemC simulation engine.

CocoTB ← mentions 70% 1e

CocoTB is mentioned as a Python-based verification tool alongside PyUVM.

OpenHW ← mentions 80% 1e

OpenHW is mentioned as having designed verification environments using UVM methodology

Functional Coverage ← part of 90% 1e

Functional coverage is a component of the UVM verification methodology

UVM Based Design Verification of a RISC-V CPU Core ← uses 100% 1e

The paper presents a UVM-based verification infrastructure for a RISC-V core.

LINKED ENTITIES

1 links

riscv-dv USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] UVM stands for Universal Verification Methodology, and RISC-V DV uses SystemVerilog with UVM for constrained-random RISC-V instruction-stream generation. Efficient Cross-Level Testing for RISC-V Processor Verification

[2] Public research summaries describe UVM as an industry-used methodology that improves verification efficiency through structured and reusable testbenches, and describe verification as consuming nearly 70% of integrated-circuit development effort. From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification

[3] Constructing UVM testbenches and generating sufficient stimuli remain challenging because of manual coding, repeated EDA tool execution, and required domain expertise. UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification

[4] RISC-V DV provides a high-level co-simulation interface using execution log files and supports several RISC-V instruction-set extensions and CSR testing capabilities. Efficient Cross-Level Testing for RISC-V Processor Verification

[5] The cited paper identifies RISC-V DV limitations: restricted instruction streams to avoid infinite loops and platform-dependent memory-access problems, plus significant performance overhead from its generic simulator-oriented design. Efficient Cross-Level Testing for RISC-V Processor Verification

[6] UVM² is summarized as an LLM-aided framework that generates UVM testbenches and refines them using coverage feedback, with reported average code and functional coverage of 87.44% and 89.58% on RTL designs up to 1.6K lines of code. From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification

[7] UVMarvel is summarized as an automated subsystem-level RTL verification framework that generates protocol-correct subsystem-level UVM testbenches using an intermediate representation and bus protocol library, and reports 95.65% average code coverage and 4.5-hour automated execution. UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification

[8] TestRIG generates random instruction sequences, executes the same sequences on a model and an implementation under test, and compares execution traces; this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[9] TestRIG uses the RISC-V Formal Interface to observe post-instruction state changes and uses Direct Instruction Injection to provide the next instruction from the test harness rather than normal program-memory fetch. Randomized Testing of RISC-V CPUs using Direct Instruction Injection