instruction class

CodeArtifact

The instruction class is a SystemVerilog transaction-level code artifact used in constrained-random microprocessor verification. It models an instruction using transaction properties, constraints over two opcode/operation objects, and standard methods for display and binary packing, and it participates in a hierarchy of transaction abstractions from operations to instructions to instruction scenarios.

First seen 5/28/2026

Last seen 6/1/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

The instruction class is a transaction-level SystemVerilog class used in constrained-random verification of microprocessors. In the described methodology, transaction abstraction is built in levels—operations, instructions, and instruction scenarios—and these levels are modeled as classes. The lower-level operation objects are created first so that higher-level stimulus descriptions can be built on top of them. ^[1]

Like other transaction classes in this methodology, the instruction class follows a three-part structure:

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

opcode class uses → 88% 2e

The instruction class builds on and uses the opcode class as a building block.

vmm_data extends → 90% 1e

The instruction class implements standard vmm_data methods, extending the VMM base class.

Transaction Abstraction part of → 92% 1e

The instruction class is a key building block of the transaction abstraction hierarchy.

Transaction Abstraction implements → 90% 1e

The instruction class is a transaction modeled as a SystemVerilog class.

LINKED ENTITIES

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vmm_data EXTENDS Extracted graph relationship

Transaction Abstraction PART_OF Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Operations, instructions, and instruction scenarios are modeled as class-based levels of transaction abstraction. Applying constrained-random verification to microprocessors

[2] A transaction class is structured around properties, constraints, and methods. Applying constrained-random verification to microprocessors

[3] Instruction-level constraints describe relationships between two opcode objects. Applying constrained-random verification to microprocessors

[4] The instruction class example encodes rules for load/store slot placement, ERET placement and pairing, and disallowing duplicate scalar-register writes within an instruction. Applying constrained-random verification to microprocessors

[5] Separate constraint blocks allow individual processor rules to be enabled or disabled, enabling legal generation or intentional rule violation for exception testing. Applying constrained-random verification to microprocessors

[6] The instruction class implements standard vmm_data methods, including methods associated with displaying and packing instructions. Applying constrained-random verification to microprocessors