ImperasDV
ToolImperasDV is a RISC-V processor verification tool that integrates fast reference models into verification flows and enables lock-step comparison of RTL against a golden reference model at instruction retirement. Evidence describes its use alongside directed ImperasTS suites, VCS simulation, Verdi debug and coverage analysis, and broader hybrid RISC-V verification flows.
First seen 5/25/2026
Last seen 8/26/2026
Evidence 16 chunks
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WIKI
Overview
ImperasDV is described as a tool that integrates fast reference models for RISC-V into verification flows. Its primary role in the provided evidence is to enable lock-step comparison of RTL against a golden reference model at instruction retirement, helping detect mismatches early in processor verification. [ImperasDV reference-model integration] [ImperasDV lock-step comparison]
Role in RISC-V verification
NEIGHBORHOOD
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47 connectionsImperasDV uses ImperasFPM as its validated reference model for lockstep comparison.
ImperasDV is published by Synopsys via their partnership with Imperas.
ImperasDV integrates with RVVI as its interface for state and event exchange.
ImperasDV enables lock-step comparison of RTL against a golden reference model at instruction retirement.
ImperasDV provides SystemVerilog interfaces and components
ImperasDV is a product published and developed by Imperas Software
ImperasDV provides the reference model and lockstep co-simulation methodology integrating with SV/UVM flows and RVVI.
ImperasDV implements the lockstep co-simulation methodology with retirement-level comparison.
ImperasDV can be used in UVM testbenches.
ImperasDV integrates with Synopsys VCS for RTL simulation in the co-simulation flow.
ImperasDV integrates with Verdi for debug of mismatches and waveform correlation.
ImperasDV integrates with VCS for RTL simulation in lockstep flows.
ImperasDV integrates fast reference models for RISC-V and uses them as a golden reference for lock-step comparison.
ImperasDV supports models to fully support the lock-step-compare verification approach.
ImperasDV is a RISC-V processor verification IP product from Imperas
ImperasDV compares RTL execution against a golden reference model to detect mismatches.
ImperasDV supports the async-lock-step-compare approach considered the gold standard in RISC-V DV.
ImperasDV is integrated with Cadence EDA SystemVerilog environments.
ImperasDV is integrated with Siemens EDA SystemVerilog environments.
ImperasTS-ISA tests are included with ImperasDV licences, creating a dependency relationship.
ImperasDV implements the RVVI-API functions for use as a RISC-V VIP
ImperasDV uses the RVVI-TRACE signal-level interface for tracer connectivity
ImperasDV implements step-and-compare methodology through RVVI-API
ImperasDV includes a configurable RISC-V reference model as a core component
core-v-verif uses ImperasDV as its verification IP for RISC-V processor verification
ImperasDV is demonstrated verifying the CV32E40X processor
ImperasDV integrates with Verdi for debug of mismatches.
ImperasDV uses RVVI interfaces for C/C++ and SystemVerilog verification flows.
ImperasDV provides C/C++ examples for use with Verilator designs.
ImperasDV provides SystemVerilog examples for use with Xcelium.
ImperasDV provides SystemVerilog examples for use with Questa.
ImperasDV is integrated with Synopsys EDA SystemVerilog environments.
The hybrid methodology uses ImperasDV for lock-step comparison against a golden reference model.
The paper describes adoption of ImperasDV as the reference model.
ImperasDV replaced the ISS as the reference model in Core-V-Verif v2.0.0.
ImperasDV functions as a true reference model.
ImperasDV is provided by Imperas Software.
ImperasDV is a front-end design verification solution.
ImperasDV uses the RVVI-TRACE interface to connect to the processor under test.
ImperasDV makes use of the open standard RISC-V Verification Interface (RVVI) for efficiency and reuse.
ImperasDV supports industry best practices including constrained-random stimulus.
ImperasDV provides a machine-generated functional coverage model for RISC-V ISA extensions.
ImperasDV handles asynchronous events using a novel pipeline synchronization technology.
ImperasDV addresses verification of DUT behavior in response to asynchronous events.
ImperasDV provides continuous comparison and checking of architectural state via the RVVI-TRACE interface.
Imperas developed ImperasDV as an integrated solution for RISC-V processor verification.
ImperasDV provides Verification IP options for RISC-V processor verification.