ImperasDV

Tool

ImperasDV is a RISC-V processor verification tool that integrates fast reference models into verification flows and enables lock-step comparison of RTL against a golden reference model at instruction retirement. Evidence describes its use alongside directed ImperasTS suites, VCS simulation, Verdi debug and coverage analysis, and broader hybrid RISC-V verification flows.

First seen 5/25/2026

Last seen 7/12/2026

Evidence 9 chunks

Wiki v1

WIKI

Overview

ImperasDV is described as a tool that integrates fast reference models for RISC-V into verification flows. Its primary role in the provided evidence is to enable lock-step comparison of RTL against a golden reference model at instruction retirement, helping detect mismatches early in processor verification. [ImperasDV reference-model integration] [ImperasDV lock-step comparison]

Role in RISC-V verification

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NEIGHBORHOOD

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RELATIONSHIPS

23 connections

Golden Reference Model uses → 98% 2e

ImperasDV integrates fast reference models for RISC-V and uses them as a golden reference for lock-step comparison.

Lockstep Co-Simulation Methodology implements → 97% 2e

ImperasDV provides the reference model and lockstep co-simulation methodology integrating with SV/UVM flows and RVVI.

Sync-Lock-Step Compare implements → 93% 2e

ImperasDV supports models to fully support the lock-step-compare verification approach.

RTL evaluates → 96% 2e

ImperasDV compares RTL execution against a golden reference model to detect mismatches.

Lock-Step Compare implements → 98% 2e

ImperasDV enables lock-step comparison of RTL against a golden reference model at instruction retirement.

Synopsys VCS depends on → 90% 2e

ImperasDV integrates with Synopsys VCS for RTL simulation in the co-simulation flow.

Verdi depends on → 90% 2e

ImperasDV integrates with Verdi for debug of mismatches and waveform correlation.

Synopsys published by → 93% 2e

ImperasDV is provided via Synopsys partnership and published by Synopsys.

ImperasTS-ISA ← depends on 88% 1e

ImperasTS-ISA tests are included with ImperasDV licences, creating a dependency relationship.

Cadence ← uses 93% 1e

ImperasDV is integrated with Cadence EDA SystemVerilog environments.

Siemens EDA ← uses 93% 1e

ImperasDV is integrated with Siemens EDA SystemVerilog environments.

Synopsys ← uses 93% 1e

ImperasDV is integrated with Synopsys EDA SystemVerilog environments.

RVVI uses → 95% 1e

ImperasDV integrates with RVVI for exchanging retire, state, and event information.

UVM uses → 93% 1e

ImperasDV integrates seamlessly with SV/UVM flows.

ImperasFPM uses → 90% 1e

ImperasDV uses ImperasFPM as its validated reference model for lockstep co-simulation.

Async-Lock-Step Compare implements → 93% 1e

ImperasDV supports the async-lock-step-compare approach considered the gold standard in RISC-V DV.

Hybrid Verification Methodology ← uses 95% 1e

The hybrid methodology uses ImperasDV for lock-step comparison against a golden reference model.

CV32E40P updates: customizing an open-source RISC-V core at industrial-grade ← uses 100% 1e

The paper describes adoption of ImperasDV as the reference model.

Core-V-Verif ← uses 100% 1e

ImperasDV replaced the ISS as the reference model in Core-V-Verif v2.0.0.

Reference Model implements → 100% 1e

ImperasDV functions as a true reference model.

Imperas Software authored by → 100% 1e

ImperasDV is provided by Imperas Software.

Imperas ← introduces 98% 1e

Imperas developed ImperasDV as an integrated solution for RISC-V processor verification.

Verification IP (VIP) implements → 97% 1e

ImperasDV provides Verification IP options for RISC-V processor verification.

LINKED ENTITIES

3 links

Lock-Step Compare IMPLEMENTS Extracted graph relationship

ImperasTS-ISA INCLUDES Extracted graph relationship

VCS INTEGRATES_WITH Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] ImperasDV reference-model integration source

[2] ImperasDV lock-step comparison source

[3] Lock-step compare definition source

[4] ImperasTS-ISA inclusion source

[5] ImperasTS family source

[6] ImperasTS self-checking suites source

[7] ImperasDV in VCS-centered flow source

[8] ImperasDV VCS and Verdi integration source

[9] ImperasDV debug efficiency source

[10] Hybrid coverage closure source