Async-Lock-Step Compare

Concept

Async-Lock-Step Compare is a dynamic (simulation-based) design verification (DV) approach, identified as Stage 4 in RISC-V processor verification methodologies. It extends sync-lock-step-compare by adding asynchronous event handling, enabling instruction-by-instruction verification of complex processor features. It is considered the gold standard for dynamic RISC-V verification.

First seen 6/21/2026

Last seen 6/21/2026

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Overview

Async-Lock-Step Compare (referred to as Stage 4 in RISC-V processor verification methodologies) is a dynamic, simulation-based design verification (DV) approach used to validate processor RTL against an instruction-accurate reference model. It is described as the gold standard in simulation-based RISC-V verification and represents the best DV environment currently available for RISC-V ^[1].

Background and Evolution

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NEIGHBORHOOD

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RELATIONSHIPS

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ImperasDV ← implements 93% 1e

ImperasDV supports the async-lock-step-compare approach considered the gold standard in RISC-V DV.

CORE-V-VERIF Testbench ← implements 95% 1e

The OpenHW CORE-V-VERIF testbench uses the Async-lock-step-compare DV approach.

LINKED ENTITIES

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ImperasDV IMPLEMENTS Extracted graph relationship

CORE-V-VERIF Testbench IMPLEMENTS Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Async-lock-step-compare DV is derived from sync-lock-step-compare to add asynchronous events. Survey of Verification of RISC-V Processors

[2] Instruction-by-instruction analysis verifies features like hardware multithreading, debug mode, interrupts, out-of-order, multiprocessor, heterogeneous arrays, and RISC-V Vectors flexibility. Survey of Verification of RISC-V Processors

[3] The approach is costly and complex because it deals with asynchronous information. Survey of Verification of RISC-V Processors

[4] CV32E40P in OpenHW 2H 2020 used the Async-lock-step-compare DV approach. Survey of Verification of RISC-V Processors

[5] The approach is considered the gold standard in dynamic (simulation-based) verification and the best DV environment currently available for RISC-V. Survey of Verification of RISC-V Processors

[6] SystemVerilog components include instruction and writeback reports, functionality checks, reference model management, and interrupt/debug coverage properties. Survey of Verification of RISC-V Processors

[7] ImperasDV provides reference models to fully support the lock-step-compare verification approach. Survey of Verification of RISC-V Processors

[8] The OpenHW CORE-V-VERIF test bench was used for CV32E40P and implements the Async-lock-step-compare DV approach. Survey of Verification of RISC-V Processors

[9] Sync-lock-step-compare runs the reference and DUT together with no data saving and a simplistic setup, depending on RTL DUT tracer features. Survey of Verification of RISC-V Processors