Skip to content
STIMSMITH

Async-Lock-Step Compare

Concept WIKI v1 · 6/21/2026

Async-Lock-Step Compare is a dynamic (simulation-based) design verification (DV) approach, identified as Stage 4 in RISC-V processor verification methodologies. It extends sync-lock-step-compare by adding asynchronous event handling, enabling instruction-by-instruction verification of complex processor features. It is considered the gold standard for dynamic RISC-V verification.

Overview

Async-Lock-Step Compare (referred to as Stage 4 in RISC-V processor verification methodologies) is a dynamic, simulation-based design verification (DV) approach used to validate processor RTL against an instruction-accurate reference model. It is described as the gold standard in simulation-based RISC-V verification and represents the best DV environment currently available for RISC-V [1].

Background and Evolution

The method derives from the industrial-quality sync-lock-step-compare technique (also called data-path lockstep-compare), in which the reference model and the Design Under Test (DUT) are run together with no data saving and a simplistic setup, requiring that both share the same timing and triggering [1]. Async-Lock-Step Compare builds on this by adding support for asynchronous events, which the synchronous variant cannot handle [1].

Verification Capabilities

Instruction-by-instruction analysis in Async-Lock-Step Compare allows verification of several advanced processor architectural features, including:

  • Hardware multithreading
  • Debug mode
  • Interrupts
  • Out-of-order (superscalar) execution
  • Multiprocessor configurations
  • Heterogeneous arrays
  • Flexibility of the RISC-V Vectors specification for AI and Deep Learning compute engines [1]

Implementation Components

SystemVerilog components used in this approach include:

  • A report of instructions and registering writebacks
  • A functionality check and reference model management
  • Properties for interrupt and debug coverage/checking [1]

Trade-offs

Async-Lock-Step Compare is considered costly and complex because it must deal with asynchronous information [1]. Its setup depends on the RTL DUT tracer features [1].

Use in OpenHW

The CV32E40P core in OpenHW 2H 2020 used the Async-lock-step-compare DV approach as illustrated in Figure 7 of the source survey [1].

Tools and Testbenches

The approach is implemented by ImperasDV, which provides integrated solutions for RISC-V processor verification for both RTL bug detection and analysis, including the use of reference models to fully support the lock-step-compare verification approach [2]. The OpenHW [CORE-V-VERIF Testbench](CORE-V-VERIF Testbench), used for CV32E40P, implements this verification approach as shown in Figure 7 of the source survey [2].

LINKED ENTITIES

2 links
ImperasDV IMPLEMENTS
CORE-V-VERIF Testbench IMPLEMENTS

CITATIONS

9 sources
9 citations
[1] Async-lock-step-compare DV is derived from sync-lock-step-compare to add asynchronous events. Survey of Verification of RISC-V Processors
[2] Instruction-by-instruction analysis verifies features like hardware multithreading, debug mode, interrupts, out-of-order, multiprocessor, heterogeneous arrays, and RISC-V Vectors flexibility. Survey of Verification of RISC-V Processors
[3] The approach is costly and complex because it deals with asynchronous information. Survey of Verification of RISC-V Processors
[4] CV32E40P in OpenHW 2H 2020 used the Async-lock-step-compare DV approach. Survey of Verification of RISC-V Processors
[5] The approach is considered the gold standard in dynamic (simulation-based) verification and the best DV environment currently available for RISC-V. Survey of Verification of RISC-V Processors
[6] SystemVerilog components include instruction and writeback reports, functionality checks, reference model management, and interrupt/debug coverage properties. Survey of Verification of RISC-V Processors
[7] ImperasDV provides reference models to fully support the lock-step-compare verification approach. Survey of Verification of RISC-V Processors
[8] The OpenHW CORE-V-VERIF test bench was used for CV32E40P and implements the Async-lock-step-compare DV approach. Survey of Verification of RISC-V Processors
[9] Sync-lock-step-compare runs the reference and DUT together with no data saving and a simplistic setup, depending on RTL DUT tracer features. Survey of Verification of RISC-V Processors