core-v-verif
Toolcore-v-verif is the OpenHW Group's functional verification project for RISC-V cores in the CORE-V family. It provides a UVM/SystemVerilog-based simulation environment initially focused on CV32E40P, supports pre-existing and generated test programs via the COREV-DV extension library, and uses Board Support Package files to align test programs with testbench resources.
First seen 5/27/2026
Last seen 7/12/2026
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Overview
core-v-verif is a functional verification project developed by the OpenHW Group to verify RISC-V cores in the CORE-V family. The public GitHub repository describes it as a "functional verification project for the CORE-V family of RISC-V cores."
The project's verification environment was initially focused on CV32E40P, a power-efficient 32-bit RISC-V core with in-order execution and a 4-stage pipeline, implementing the RV32IMCZifencei ISA extensions. The evidence describes core-v-verif as providing a simulation environment for the CV32E40P RTL core, and notes that the environment was intended to be adapted for additional CORE-V cores such as CV32E40X, CV32E40S, CVA6, and future OpenHW roadmap cores.
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20 connectionsThe paper discusses Core-V-Verif as a state-of-the-art verification project.
Core-V-Verif is used to verify the CV32E40P core.
Core-V-Verif uses UVM for developing verification test plans and environment.
Core-V-Verif uses class libraries based on SystemVerilog.
Core-V-Verif incorporates a random instruction stream generator for test programs.
Core-V-Verif uses a Board Support Package to align test program resources with DUT resources.
The paper describes reuse of Core-V-Verif for verification.
Core-V-Verif follows the UVM standard.
Core-V-Verif integrates a reference model for step&compare verification.
The first generation of Core-V-Verif used an ISS from Imperas Software as the reference model.
step&compare was used in Core-V-Verif to keep DUT and ISS synchronized.
ImperasDV replaced the ISS as the reference model in Core-V-Verif v2.0.0.
Core-V-Verif is developed and maintained by the OpenHW Group.
Core-V-Verif was originally developed for and used to verify CV32E40P.
core-v-verif uses riscv-dv as-is for core verification.
core-v-verif includes and uses COREV-DV extensions.
COREV-DV is a component library within the core-v-verif verification environment.
CORE-V-VERIF is an open-source SV/UVM environment for RISC-V core verification.
CORE-V-VERIF is used to verify RISC-V cores like the CV32E40P.
CORE-V-VERIF is attributed to OpenHW Group as its originating organization.
LINKED ENTITIES
2 linksCITATIONS
16 sources16 citations — click to expand
[1] core-v-verif is a functional verification project developed by the OpenHW Group to verify the RISC-V cores of the CORE-V family. UVM based design verification of a RISC-V CPU core - POLITesi
[2] The verification environment is not specific to any single EDA vendor, using class libraries based on SystemVerilog. UVM based design verification of a RISC-V CPU core - POLITesi
[3] Initially the focus was to verify the CV32E40P, a 32-bit RISC-V core with in-order execution and a 4-stage pipeline implementing the RV32IMCZifencei ISA extensions. UVM based design verification of a RISC-V CPU core - POLITesi
[4] The environment was intended to be adapted for additional CORE-V cores including CV32E40X, CV32E40S, CVA6 and future cores on the OpenHW roadmap. UVM based design verification of a RISC-V CPU core - POLITesi
[5] Co-simulation uses a particular version of Spike and the RISC-V Formal Interface (RVFI) provides information about retired instructions and instructions that produce synchronous traps for checking. UVM based design verification of a RISC-V CPU core - POLITesi
[6] The CORE-V UVM environment supports five types of test programs: pre-existing self-checking, pre-existing not self-checking, generated self-checking, generated not self-checking, and none. UVM based design verification of a RISC-V CPU core - POLITesi
[7] Pre-existing self-checking programs and generated non-self-checking programs are expected to predominate. UVM based design verification of a RISC-V CPU core - POLITesi
[8] Checker-monitors signal an error condition with uvm_error and cause a simulation to fail independently of what the test program writes to the status-flags virtual peripheral. UVM based design verification of a RISC-V CPU core - POLITesi
[9] COREV-DV is a library of extensions to the Google riscv-dv instruction stream generator, residing at $CORE_V_VERIF/lib/corev-dv, with per-core extensions under $CORE_V_VERIF/$COREV_CORE/env/corev-dv. COREV-DV — CORE-V Verification Strategy documentation
[10] A specific hash of riscv-dv is cloned to $CORE_V_VERIF/$COREV_CORE/vendor_lib/riscv-dv when a Make target requires it, and the compile Makefiles generate the core-specific version of corev-dv. COREV-DV — CORE-V Verification Strategy documentation
[11] $CORE_V_VERIF/lib/corev-dv/corev_asm_program_gen.sv overrides riscv_gen_program_header::gen_program_header() to enforce common symbols required by the BSP, and each core may need core-specific extensions. COREV-DV — CORE-V Verification Strategy documentation
[12] Board Support Package files include linker scripts, control/status-register configuration files, and assembly files providing the minimum startup needed to run a C program; test-program environment files must match testbench resources. UVM based design verification of a RISC-V CPU core - POLITesi
[13] All UVM tests in the CV32E environment extend the base test class uvmt_cv32_base_test_c, which directly extends uvm_test. UVM based design verification of a RISC-V CPU core - POLITesi
[14] A typical CORE-V UVM test extends three time-consuming tasks: reset phase (often calling super.reset_phase() to invoke the default reset sequence), configure phase (loading pre-compiled programs into instruction memory when required), and run phase (containing the procedural test code). UVM based design verification of a RISC-V CPU core - POLITesi
[15] The cited run-flow raises an objection, asserts the core's fetch_en input, waits for completion, and drops the objection. UVM based design verification of a RISC-V CPU core - POLITesi
[16] The public GitHub repository openhwgroup/core-v-verif is described as the functional verification project for the CORE-V family of RISC-V cores, with the repository language listed as Assembly. openhwgroup/core-v-verif