Core-V-Verif

Tool

Core-V-Verif is OpenHW Group’s functional verification project for the CORE-V family of RISC-V cores. It provides a UVM/SystemVerilog-based simulation environment initially focused on CV32E40P, supports pre-existing and generated test programs, and uses Board Support Package files to align software tests with testbench resources.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

Core-V-Verif is a functional verification project developed by the OpenHW Group to verify RISC-V cores in the CORE-V family. The public repository describes it as a functional verification project for the CORE-V family of RISC-V cores.

The project’s verification environment was initially focused on CV32E40P, a 32-bit RISC-V core with in-order execution and a 4-stage pipeline. The cited thesis describes Core-V-Verif as providing a simulation environment for the CV32E40P RTL core, and notes that the environment was intended to be adapted for additional CORE-V cores such as CV32E40X, CV32E40S, CVA6, and future OpenHW roadmap cores.

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RELATIONSHIPS

6 connections

UVM Based Design Verification of a RISC-V CPU Core ← mentions 95% 2e

The paper discusses Core-V-Verif as a state-of-the-art verification project.

CV32E40P evaluates → 100% 1e

Core-V-Verif is used to verify the CV32E40P core.

UVM uses → 100% 1e

Core-V-Verif uses UVM for developing verification test plans and environment.

SystemVerilog uses → 95% 1e

Core-V-Verif uses class libraries based on SystemVerilog.

Random Instruction Generator uses → 95% 1e

Core-V-Verif incorporates a random instruction stream generator for test programs.

Board Support Package uses → 95% 1e

Core-V-Verif uses a Board Support Package to align test program resources with DUT resources.

LINKED ENTITIES

6 links

Random Instruction Generator USES Extracted graph relationship

UVM Based Design Verification of a RISC-V CPU Core MENTIONS Extracted graph relationship

CV32E40P EVALUATES Extracted graph relationship

UVM USES Extracted graph relationship

SystemVerilog USES Extracted graph relationship

Board Support Package USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Core-V-Verif is a functional verification project for the CORE-V family of RISC-V cores, developed by OpenHW Group. openhwgroup/core-v-verif

[2] Core-V-Verif initially focused on CV32E40P and provides a simulation environment for the CV32E40P RTL core, with adaptation planned for other CORE-V cores. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[3] Core-V-Verif uses UVM and SystemVerilog-based class libraries, and is described as not specific to a single EDA vendor. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[4] The Core-V-Verif UVM environment supports pre-existing and generated test programs, self-checking and non-self-checking modes, and a no-program mode. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[5] Core-V-Verif incorporates a random instruction stream generator to generate many test programs. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[6] Checker-monitors can fail a simulation by signaling uvm_error independently of status written by a test program. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[7] The core testbench implements virtual peripherals at specific data-bus addresses and uses Board Support Package files such as linker scripts, CSR configuration files, and startup assembly files to align tests with supported resources. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[8] In the CV32E environment, UVM tests should extend uvmt_cv32_base_test_c, and a typical run flow raises an objection, asserts fetch_en, waits for completion, and drops the objection. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[9] The public GitHub repository is openhwgroup/core-v-verif and its public metadata describes it as a functional verification project for CORE-V RISC-V cores. openhwgroup/core-v-verif