UVM Based Design Verification of a RISC-V CPU Core
Paper“UVM Based Design Verification of a RISC-V CPU Core” is a technical work on CPU-core verification methods, centered on UVM/SystemVerilog verification practice for RISC-V designs. The supplied evidence shows that it motivates CPU verification as a difficult state-space problem, explains verification planning and UVM testbench concepts, and surveys open-source RISC-V verification environments such as Ibex and Core-V-Verif, including co-simulation with Spike, random instruction generation, coverage planning, scoreboards, BSP-compatible test programs, and RVFI-based checking.
First seen 5/27/2026
Last seen 5/28/2026
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Overview
“UVM Based Design Verification of a RISC-V CPU Core” is a technical work available as a POLITesi PDF that discusses verification of RISC-V CPU cores using UVM-oriented design-verification practices. The work frames CPU verification as a demanding problem because processors are complex state machines with many states and corner cases; verification must check instruction correctness, exception handling, memory accesses, timing behavior, and expected functional outcomes. It also notes that the practical number of possible test cases can be far beyond exhaustive exploration, making systematic verification strategy essential. [C1]
Verification planning
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27 connectionsThe paper uses a scoreboard for checking functional correctness in the testbench.
The paper uses constrained random verification as part of its verification methodology.
The paper discusses formal verification as a technique used in CPU verification.
The paper presents a UVM-based testbench for RISC-V verification.
The paper uses the RISC-V compliance test suite for instruction set compliance testing.
The paper discusses the Ibex Core as a state-of-the-art RISC-V CPU verification example.
The paper discusses Core-V-Verif as a state-of-the-art verification project.
The paper employs co-simulation methodology using Spike as a reference model.
The paper uses specifically designed direct tests for RISC-V core verification.
The paper uses benchmarks to evaluate the functional performance of the RISC-V core.
The paper integrates the RISC-V toolchain as part of its verification infrastructure.
The paper includes fuzzing as part of its experimental evaluation.
The paper includes AHB verification IP in its testbench architecture.
The paper evaluates the RISC-V core using the Dhrystone benchmark.
The paper evaluates the RISC-V core using the Coremark benchmark.
The paper implements a functional coverage model in the verification infrastructure.
The paper discusses and employs a verification test plan as part of the verification infrastructure.
The paper uses the RISC-V Formal Interface to provide information about retired instructions for co-simulation checking.
The thesis paper is authored by Renato Occhineri.
The paper mentions CV32E40P as the primary target core of the Core-V-Verif environment.
Franco Zappa is the academic advisor of the thesis.
The paper presents a UVM-based verification infrastructure for a RISC-V core.
The paper uses SystemVerilog for the verification infrastructure.
The paper targets verification of a RISC-V CPU core.
The paper incorporates Spike as a RISC-V ISS for co-simulation validation.
The paper includes a random instruction generator in the verification infrastructure.
The paper employs coverage-driven verification enabled by UVM and SystemVerilog.
LINKED ENTITIES
27 linksRenato Occhineri AUTHORED_BY Extracted graph relationship
Franco Zappa AUTHORED_BY Extracted graph relationship
UVM USES Extracted graph relationship
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Dhrystone EVALUATES Extracted graph relationship
Coremark EVALUATES Extracted graph relationship
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Verification Test Plan USES Extracted graph relationship
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formal verification USES Extracted graph relationship
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Ibex Core MENTIONS Extracted graph relationship
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CITATIONS
8 sources8 citations — click to expand
[1] C1: The work motivates CPU verification as difficult because CPUs are complex state machines requiring checks of instruction correctness, exceptions, memory accesses, timing, and functional outcomes, while exhaustive testing is impractical. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] C2: A verification test plan derives from the design specification, records features/configurations and combinations to verify, and commonly uses constrained-random or coverage-driven simulation, with formal verification for selected areas. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[3] C3: UVM is presented as a SystemVerilog class framework with drivers, monitors, stimulus generators, scoreboards, sequence items, components, factory substitution, and phased execution. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[4] C4: The work states that proprietary CPU verification practices are often opaque, while open-source RISC-V enables examination of production-ready verification processes. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[5] C5: Ibex is described as a SystemVerilog 32-bit RISC-V core verified with a UVM-based co-simulation testbench using Spike, RISC-DV-generated binaries, randomized stimuli, and test/coverage planning. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[6] C6: Core-V-Verif is described as an OpenHW functional-verification project for CORE-V RISC-V cores, initially focused on CV32E40P, using UVM/SystemVerilog class libraries in a vendor-independent simulation environment. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[7] C7: Core-V-Verif test programs must be BSP-compatible, may be pre-existing or generated and self-checking or non-self-checking, and checker-monitors can fail simulations by issuing uvm_error. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[8] C8: The evidence states that Spike is required for the co-simulation system and that RVFI supplies information about retired instructions and synchronous traps for checking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi