Direct Tests

Concept

Direct tests are explicitly designed verification tests used in the UVM-based verification infrastructure for a RISC-V CPU core. In the cited thesis, they complement compliance tests, benchmarks, fuzzing, and random instruction generation to evaluate functional correctness and performance under selected scenarios.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

In the available evidence, direct tests refer to specifically designed tests included in a UVM-based verification infrastructure for a RISC-V CPU core. The thesis describes these tests as part of a broader testing strategy that also includes the RISC-V compliance test suite, a random instruction generator, benchmarks, Spike-based instruction checking, and coverage-driven verification components. [C1]

Role in RISC-V core verification

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UVM Based Design Verification of a RISC-V CPU Core ← uses 100% 1e

The paper uses specifically designed direct tests for RISC-V core verification.

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

CITATIONS

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[1] The UVM-based RISC-V verification infrastructure includes specifically designed direct tests together with other testing components. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[2] The direct tests and benchmarks are tailored for the RISC-V core and aim to evaluate functional performance and correctness under various scenarios and conditions. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[3] Direct tests appear as a dedicated subsection in the thesis experimental evaluation, alongside compliance tests, benchmarks, and fuzzing. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[4] The verification infrastructure incorporates Spike for validating instruction execution and supports coverage-driven verification, reusable components, and high-performance simulation. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi