Overview

In the available evidence, direct tests refer to specifically designed tests included in a UVM-based verification infrastructure for a RISC-V CPU core. The thesis describes these tests as part of a broader testing strategy that also includes the RISC-V compliance test suite, a random instruction generator, benchmarks, Spike-based instruction checking, and coverage-driven verification components. [C1]

Role in RISC-V core verification

The direct tests were tailored for the target RISC-V core and were intended to evaluate both functional performance and correctness under different scenarios and conditions. [C2] This places them alongside benchmarks and random testing as one of the stimulus sources used to exercise the design during simulation-based verification.

Placement in the experimental evaluation

The thesis table of contents lists Direct tests as a dedicated subsection of the experimental evaluation, following instruction-set compliance testing and preceding benchmarks such as Dhrystone and CoreMark. [C3] This indicates that direct tests were treated as a distinct evaluation category within the verification campaign rather than being folded into compliance, benchmark, or fuzzing activities.

Relationship to the broader infrastructure

The same infrastructure incorporates Spike, a RISC-V instruction set simulator, to validate correct instruction execution, and uses UVM/SystemVerilog methodology to support reusable components, coverage-driven verification, and high-performance simulation. [C4] Within that infrastructure, direct tests contribute targeted, designed scenarios that complement generated and standardized test inputs.