Scoreboard

Concept

In the provided RISC-V UVM verification evidence, a scoreboard is a verification checking component used within a testbench to help ensure functional correctness. The material treats scoreboards as one possible implementation of checks alongside interface assertions and embedded assertions, and shows a Scoreboard as a named component in a CORE-V-VERIF-style environment.

First seen 5/27/2026

Last seen 6/8/2026

Evidence 5 chunks

Wiki v2

WIKI

Definition

A scoreboard is a verification checking mechanism used in a hardware verification testbench. In the cited RISC-V CPU-core verification material, checks intended to ensure functional correctness can be implemented as scoreboards, interface assertions, or embedded assertions inside RTL or verification components.

Role in a UVM testbench

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RELATIONSHIPS

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UVM Based Design Verification of a RISC-V CPU Core ← uses 95% 2e

The paper uses a scoreboard for checking functional correctness in the testbench.

Testbench part of → 90% 1e

A testbench includes a scoreboard as a checking component.

UVM testbench part of → 1e

The UVM Testbench contains a Scoreboard as a sub-component.

LINKED ENTITIES

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

Core-V-Verif USES Extracted graph relationship

Testbench PART_OF Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Scoreboards are one possible implementation of functional correctness checks, alongside interface assertions and embedded assertions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] UVM provides SystemVerilog classes for building testbenches, including drivers, monitors, stimulus generators, and scoreboards. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] A UVM component is described as a self-contained unit of verification logic that performs a specific task within the verification environment. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] A verification test plan should capture checking mechanisms, what is being verified, how it will be verified, and a block diagram of testbench components, hierarchy, and stimulus patterns. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] The CORE-V-VERIF overview shown in the thesis includes a Scoreboard as a named environment component. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] The CORE-V-VERIF-related testbench material describes memory-module virtual peripherals and BSP files used to align test-program resources with resources supported by the DUT. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] The CORE-V-VERIF UVM environment supports pre-existing or generated test programs and self-checking or non-self-checking test programs. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] Checker-monitors outside the status-flags virtual peripheral must signal errors with uvm_error, causing simulation failure independently of status-flag writes. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[9] The thesis table of contents includes a dedicated section titled 4.2.5 Scoreboard. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi