Testbench

Concept

A testbench is the simulation environment used to verify a design under test (DUT), especially in RTL and digital circuit verification. In modern SystemVerilog/UVM practice, it is built from reusable components such as drivers, monitors, stimulus generators, scoreboards, memory models, agents, tests, and coverage collectors. A good testbench is derived from a verification test plan, supplies stimulus, checks functional correctness, records coverage, and may compare DUT behavior against a reference model or self-checking test program.

First seen 5/27/2026

Last seen 6/6/2026

Evidence 11 chunks

Wiki v1

WIKI

Overview

A testbench is the verification environment around a design under test (DUT). In digital circuit design, testbenches are described as a cornerstone of simulation-based hardware verification: they provide the infrastructure for exercising the DUT, observing its behavior, and deciding whether a simulation passes or fails.

In a planned verification flow, the testbench is not an isolated piece of code. It is typically derived from a verification test plan that records both what must be verified and how it will be verified. The plan should describe the stimulus infrastructure, randomization controls, sequences and tests, checking mechanisms, component hierarchy, and stimulus patterns so that the implementation can be built with fewer integration issues.

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RELATIONSHIPS

7 connections

Tandem Simulation ← uses 90% 2e

Tandem simulation requires testbenches for both ILEM and RTEM

Instruction-Level Execution Model (ILEM) ← uses 90% 2e

ILEM requires instruction-by-instruction testbenches

RTL-Based Execution Model (RTEM) ← uses 90% 2e

RTEM requires cycle-by-cycle testbenches

UVM Based Design Verification of a RISC-V CPU Core ← uses 100% 2e

The paper presents a UVM-based testbench for RISC-V verification.

Hierarchical Constrained-Random Test Generation ← uses 1e

Hierarchical constrained-random test generation is integrated into a testbench environment for performance measurement.

Scoreboard ← part of 90% 1e

A testbench includes a scoreboard as a checking component.

Functional Coverage ← part of 85% 1e

A testbench includes functional coverage mechanisms.

LINKED ENTITIES

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UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

Scoreboard PART_OF Extracted graph relationship

Functional Coverage PART_OF Extracted graph relationship

CITATIONS

11 sources

11 citations — click to expand

[1] Digital-circuit testbenches are central to simulation-based hardware verification. AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

[2] A verification test plan should capture what features and configurations must be verified and should guide stimulus infrastructure, checking mechanisms, and testbench architecture. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] Functional verification commonly uses simulation with constrained-random or coverage-driven approaches, while formal verification may be applied selectively. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] UVM provides SystemVerilog classes for building testbenches with drivers, monitors, stimulus generators, scoreboards, and sequence items. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] UVM phases group testbench execution into build, run-time, and clean-up phases. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] In the Ibex verification environment, the testbench executes programs from memory, compares the core trace against the Spike ISS trace, and collects instruction and operand coverage. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] The Ibex testbench includes memory-interface agents, an interrupt agent, and a memory model that loads a compiled assembly program and serves instruction/data memory requests. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] In CORE-V-Verif, the testbench memory module implements virtual peripherals, and BSP files align test-program resources with DUT and testbench resources. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[9] CORE-V-Verif supports pre-existing, generated, self-checking, non-self-checking, and no-program UVM test modes, and checker-monitors can fail simulations by issuing uvm_error independently of program status flags. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[10] AutoBench is an LLM-based HDL testbench generator that uses a hybrid testbench structure and self-checking system and reports a 57% pass@1 improvement over direct LLM generation. AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

[11] LLM-aided testbench generation research has used EDA-tool feedback with GPT-3.5 and GPT-4 to iteratively refine finite-state-machine testbenches and improve test coverage. LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines