CV32E40P

Tool

CV32E40P is an OpenHW Group 32-bit RISC-V CPU core implemented in SystemVerilog. The public GitHub repository characterizes it as an in-order, 4-stage RV32IMFCXpulp core derived from the RI5CY core of PULP-Platform. Within the Core-V-Verif functional verification environment, the core implements the RV32IMCZifencei ISA extensions and is the initial verification focus of that UVM/SystemVerilog-based testbench. CV32E40P is verified using COREV-DV, the Core-V-Verif-specific extension of Google's riscv-dv instruction stream generator.

First seen 5/27/2026

Last seen 6/18/2026

Evidence 4 chunks

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Overview

CV32E40P is a RISC-V CPU core from the OpenHW Group. The public OpenHW GitHub repository describes it as an in-order, 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform. The repository is written primarily in SystemVerilog.

A 2024 UVM verification study describes CV32E40P as a power-efficient 32-bit RISC-V core using in-order execution with a 4-stage pipeline. The same study notes that the core was already present in several commercial SoC designs, including IoT devices and a general-purpose 32-bit microcontroller, characterizing it as "small in size but big in popularity."

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RELATIONSHIPS

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UVM Based Design Verification of a RISC-V CPU Core ← mentions 90% 1e

The paper mentions CV32E40P as the primary target core of the Core-V-Verif environment.

Core-V-Verif ← evaluates 100% 1e

Core-V-Verif is used to verify the CV32E40P core.

RISC-V implements → 100% 1e

CV32E40P is a 32-bit RISC-V core implementing the RISC-V ISA.

COREV-DV uses → 90% 1e

CV32E40P has core-specific extensions to COREV-DV as an example case.

LINKED ENTITIES

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COREV-DV USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] CV32E40P is an in-order, 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, with its repository written in SystemVerilog. openhwgroup/cv32e40p

[2] CV32E40P is a power-efficient 32-bit RISC-V core using in-order execution with a 4-stage pipeline, and is the initial focus of the Core-V-Verif functional verification project, which targets the CORE-V family of cores from OpenHW. UVM based design verification of a RISC-V CPU core - POLITesi

[3] The Core-V-Verif environment for CV32E40P is based on the RISC-V specification and implements the RV32IMCZifencei ISA extensions. UVM based design verification of a RISC-V CPU core - POLITesi

[4] The Core-V-Verif testbench uses UVM and SystemVerilog class libraries, making it not specific to any single EDA vendor, and provides a simulation environment for the CV32E40P RTL core. UVM based design verification of a RISC-V CPU core - POLITesi

[5] The Core-V-Verif memory module implements virtual peripherals by responding to reads/writes at specific addresses on the data bus, and the testbench uses a Board Support Package (BSP) with linker scripts, CSR configuration files, and assembly files needed to run C programs. UVM based design verification of a RISC-V CPU core - POLITesi

[6] The Core-V-Verif UVM environment supports four (plus a 'none') categories of test programs distinguished by pre-existing/generated and self-checking/non-self-checking, with many RI5CY-inherited programs being pre-existing and self-checking. UVM based design verification of a RISC-V CPU core - POLITesi

[7] The CV32E UVM environment defines a base test class uvmt_cv32_base_test_c extended from uvm_test, with a typical run flow that raises an objection, asserts fetch_en, waits for completion, and drops the objection; the base test customizes reset, configure, and run phases. UVM based design verification of a RISC-V CPU core - POLITesi

[8] COREV-DV is the Core-V-Verif library of extensions to Google's riscv-dv instruction stream generator; it is implemented as SystemVerilog classes extending uvm_object, with non-core-specific extensions in $CORE_V_VERIF/lib/corev-dv and core-specific extensions in $CORE_V_VERIF/$COREV_CORE/env/corev-dv (with CV32E40P given as the example core). COREV-DV — CORE-V Verification Strategy documentation

[9] To run the co-simulation system a particular version of Spike is required, and the RISC-V Formal Interface (RVFI) is used to provide information about retired instructions and instructions that produce synchronous traps for checking. UVM based design verification of a RISC-V CPU core - POLITesi