CV32E40P

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CV32E40P is an OpenHW Group SystemVerilog RISC-V CPU core described as an in-order, 4-stage, 32-bit core based on RI5CY/PULP work. It is an early focus target of the Core-V-Verif functional verification environment, which provides UVM-based simulation support for the core.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

CV32E40P is a RISC-V CPU core from the OpenHW Group. The public OpenHW GitHub repository describes it as an in-order, 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform. The repository is written primarily in SystemVerilog.

A 2024 UVM verification study describes CV32E40P as a power-efficient 32-bit RISC-V core using in-order execution with a 4-stage pipeline. The same study notes that the core was already present in several commercial SoC designs, including IoT devices and a general-purpose 32-bit microcontroller.

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RELATIONSHIPS

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UVM Based Design Verification of a RISC-V CPU Core ← mentions 90% 1e

The paper mentions CV32E40P as the primary target core of the Core-V-Verif environment.

Core-V-Verif ← evaluates 100% 1e

Core-V-Verif is used to verify the CV32E40P core.

RISC-V implements → 100% 1e

CV32E40P is a 32-bit RISC-V core implementing the RISC-V ISA.

LINKED ENTITIES

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UVM Based Design Verification of a RISC-V CPU Core MENTIONS Extracted graph relationship

Core-V-Verif EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

CITATIONS

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8 citations — click to expand

[1] CV32E40P is described by its public GitHub repository as an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, implemented primarily in SystemVerilog. openhwgroup/cv32e40p

[2] CV32E40P is a power-efficient 32-bit RISC-V core using in-order execution with a 4-stage pipeline and has been used in commercial SoC designs including IoT devices and a general-purpose 32-bit microcontroller. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[3] Core-V-Verif is an OpenHW functional verification project for CORE-V RISC-V cores and initially focused on verifying CV32E40P. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[4] The Core-V-Verif simulation environment for CV32E40P is UVM-based, uses SystemVerilog class libraries, and is not specific to one EDA vendor. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[5] In the Core-V-Verif context, the CV32E40P RTL core is described as based on the RISC-V specification and implementing RV32IMCZifencei ISA extensions. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[6] The Core-V-Verif testbench memory module implements virtual peripherals by responding to data-bus reads or writes at specific addresses, and BSP files align test-program resources with DUT-supported resources. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[7] Core-V-Verif supports pre-existing and generated test programs, self-checking and non-self-checking test programs, and tests with no program; it also includes a random instruction stream generator. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[8] The CV32E UVM environment defines uvmt_cv32_base_test_c as a base test derived from uvm_test, and a typical run flow raises an objection, asserts fetch_en, waits for completion, and drops the objection. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi