Fuzzing
ConceptFuzzing is a testing technique in which a target is repeatedly exercised with modified or randomized inputs to surface bugs and security vulnerabilities. Originally a software-testing method, it has been extended to automated grammar learning, library fuzz-driver generation, and hardware/RTL verification, including FPGA-accelerated frameworks such as HWFuzz for RISC-V processors.
First seen 5/27/2026
Last seen 7/11/2026
Evidence 8 chunks
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Overview
Fuzzing is a testing technique that repeatedly exercises an application with modified, or "fuzzed," inputs. In the software-security setting described by Learn&Fuzz, its goal is to find security vulnerabilities in input-parsing code. The approach generates large volumes of random and often invalid inputs to trigger unexpected behavior [1].
Fuzzing has traditionally served as a software testing tool, but has more recently been adapted to verify hardware circuits, with modifications tailored to processor verification [2].
NEIGHBORHOOD
3 nodes · 3 edgesgraph · Fuzzing · depth=1
RELATIONSHIPS
4 connections Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging compares with → 85% 2e
The paper discusses fuzzing as a related technique compared to its approach.
The paper includes fuzzing as part of its experimental evaluation.
OSS-Fuzz is an industry-based fuzzing platform
HWFuzz is a fuzzing-based verification framework.
LINKED ENTITIES
1 linksCITATIONS
11 sources11 citations — click to expand
[1] Fuzzing consists of repeatedly testing an application with modified, or fuzzed, inputs with the goal of finding security vulnerabilities in input-parsing code. Learn&Fuzz: Machine Learning for Input Fuzzing
[2] Learn&Fuzz uses sample inputs and neural-network-based statistical machine-learning techniques to automatically generate an input grammar for fuzzing, with a case study on PDF inputs and the PDF parser embedded in Microsoft Edge, using a learned input probability distribution to guide fuzzing. Learn&Fuzz: Machine Learning for Input Fuzzing
[3] Crafting high-quality fuzz drivers is time-consuming and requires deep library understanding; PromptFuzz is a coverage-guided fuzzer that iteratively generates fuzz drivers using instructive program generation, erroneous program validation, coverage-guided prompt mutation, and constrained fuzzer scheduling. Prompt Fuzzing for Fuzz Driver Generation
[4] PromptFuzz-generated fuzz drivers achieved 1.61× and 1.63× higher branch coverage than OSS-Fuzz and Hopper on 14 real-world libraries, and detected 33 genuine new bugs out of 49 crashes, 30 of which were confirmed by their respective communities. Prompt Fuzzing for Fuzz Driver Generation
[5] Fuzzing has traditionally served as software testing tools that identify security vulnerabilities and bugs by generating large volumes of random and often invalid input data, and has recently been adapted to verify hardware circuits with processor-specific modifications. HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
[6] RFuzz was the first tool to apply fuzzing to RTL functional verification, but limited to small-scale design; DifuzzRTL improved performance with a cycle-accurate, scalable RTL coverage metric; TheHuzz and Cascade further optimized instruction generation and efficiency. HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
[7] HWFuzz is a high-performance fuzzing-based verification framework for RISC-V processors that uses a hardware fuzzer IP for fast coverage-directed stimulus generation and an end-to-end iterative verification framework; it achieves 2.03× speedup over conventional software approaches via FPGA acceleration. HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
[8] HWFuzz uses the Zynq UltraScale+ PL+PS architecture: PL hosts the hardware fuzzer IP and RISC-V DUT, PS runs the software reference model, and ENCORE's differential checking compares DUT and reference results dynamically. HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
[9] HWFuzz automatically instruments fine-grained synthesizable coverpoints into the DUT at compile time, collecting coverage directly from the FPGA at runtime to feed back into stimulus generation. HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
[10] The HWFuzz hardware fuzzer IP has two modes — random (selects instructions purely at random) and mutation (adjusts operands and context of previously generated stimuli, preferentially modifying those most likely to maximize coverage from a hardware-stored stimuli/coverage corpus). HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification
[11] HWFuzz generates two types of stimuli — instructions and data — stored in a designated DDR region serving as the testing environment for the DUT. HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification