HWFuzz

Tool

First seen 7/11/2026

Last seen 7/11/2026

Evidence 4 chunks

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RV64G extension uses → 100% 2e

HWFuzz is configured to support RV64G extension.

FPGA acceleration uses → 100% 2e

HWFuzz uses FPGA acceleration to speed up the verification process.

Design Under Test (DUT) uses → 100% 2e

HWFuzz applies stimuli to a design-under-test and collects coverage data from it.

DiFuzzRTL ← compares with 80% 2e

HWFuzz is compared against DifuzzRTL as a prior hardware fuzzing approach.

hardware fuzzer IP uses → 100% 1e

HWFuzz includes a hardware fuzzer IP as a core component.

Mutation-Based Fuzzing uses → 100% 1e

HWFuzz uses mutation mode to modify previously generated stimuli.

random instruction generation uses → 100% 1e

HWFuzz uses a random mode that selects instructions purely at random.

stimuli packing uses → 90% 1e

HWFuzz packs stimuli (instructions and data) into DDR regions for DUT verification.

stimuli constraints uses → 90% 1e

HWFuzz applies hardware constraints on instructions to improve executability.

instruction injector uses → 90% 1e

HWFuzz uses an instruction injector to insert auxiliary instructions providing register values.

coverage corpus uses → 90% 1e

HWFuzz stores generated stimuli and coverage data in a corpus to guide future fuzzing iterations.

synthesizable coverpoints uses → 100% 1e

HWFuzz automatically instruments synthesizable coverpoints into the DUT during compilation.

differential checking uses → 100% 1e

HWFuzz reuses differential checking capability from ENCORE to compare DUT and reference model results.

ENCORE uses → 100% 1e

HWFuzz reuses differential checking capability from ENCORE.

Zynq UltraScale+ uses → 100% 1e

HWFuzz leverages the Zynq UltraScale+ FPGA architecture for its implementation.

Rocket Core evaluates → 100% 1e

HWFuzz uses Rocket Core as the design-under-test in its evaluations.

RV64I extension uses → 100% 1e

HWFuzz is configured to support RV64I extension.

RISC-V Processor Verification uses → 100% 1e

HWFuzz targets RISC-V processor verification as its primary application domain.

TheHuzz compares with → 80% 1e

HWFuzz is compared against TheHuzz as a prior hardware fuzzing approach.

Cascade ← compares with 90% 1e

HWFuzz addresses limitations that Cascade handled via software, opting instead for hardware constraints.

RFUZZ compares with → 70% 1e

RFUZZ is mentioned as a prior coverage-directed hardware fuzzing approach that HWFuzz advances beyond.

HWFuzz: An FPGA-Accelerated Fuzzing Framework for Efficient RISC-V Verification ← introduces 100% 1e

The paper introduces HWFuzz as a new FPGA-accelerated fuzzing framework for RISC-V verification.

hardware fuzzer IP implements → 100% 1e

HWFuzz implements a synthesizable and highly configurable hardware fuzzer IP.

Fuzzing uses → 100% 1e

HWFuzz is a fuzzing-based verification framework.

coverage-directed generation uses → 100% 1e

HWFuzz uses coverage-directed generation to produce better instruction stimuli.

RISC-V instruction sequence generation uses → 100% 1e

HWFuzz rapidly generates RISC-V instruction sequences as part of its verification approach.